COMPUTING PLATFORM WITH INTERFACE BASED ERROR INJECTION

• US 20140053024A1
• Filed: 11/21/2012
• Published: 02/20/2014
• Est. Priority Date: 11/22/2011
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Kumar, Mohan, Jayakumar, Sarathy, Vargas, Jose Andy
• Granted Patent: US 9,594,570 B2
• Time in Patent Office: Days
• US Class Current: 714/32
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/28 Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 11/3024 where the computing system component is a central processing unit [CPU]
• CPC Class Codes: G06F 11/3409 for performance assessment
• CPC Class Codes: G06F 11/3447 Performance evaluation by modeling
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 11/3664 Environments for testing or debugging software
• CPC Class Codes: G06F 11/3672 Test management
• CPC Class Codes: G06F 11/3688 for test execution, e.g. scheduling of test suites
• CPC Class Codes: G06F 15/7871 Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
• CPC Class Codes: G06F 16/2282 Tablespace storage structures; Management thereof
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 2209/501 Performance criteria
• CPC Class Codes: G06F 9/22 : Microcontrol or microprogram arrangements
• CPC Class Codes: G06F 9/30098 : Register arrangements
• CPC Class Codes: G06F 9/3012 : Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/384 : Register renaming
• CPC Class Codes: G06F 9/44 : Arrangements for executing specific programs
• CPC Class Codes: G06F 9/4401 : Bootstrapping security arrangements therefor G06F21/57
• CPC Class Codes: G06F 9/4403 : Processor initialisation
• CPC Class Codes: G06F 9/4418 : Suspend and resume; Hibernate and awake
• CPC Class Codes: G06F 9/445 : Program loading or initiating bootstrapping G06F9/4401; security arrangements for program loading or initiating G06F21/57
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In some embodiments, a PPM interface for a computing platform may be provided with functionality to facilitate, to an OS through the PPM interface, hardware component error injection.

Claims

1. A computing platform, comprising:

non-volatile memory having a firmware boot program; and

a CPU to execute the firmware boot program when the CPU is reset, the firmware boot program including instructions to create PPM interface data structures including an error injection table structure to provide error injection services to an OS.

2. The computing platform of claim 1, in which the error injection table structure comprises a table with supported error injection actions.

3. The computing platform of claim 1, in which the error injection table structure comprises a table showing the layout of an injection instruction entry.

4. The computing platform of claim 1, in which the error injection table structure comprises a table showing instruction flags.

5. The computing platform of claim 1, in which the error injection table structure comprises a table listing injection instructions supported for injection instruction entries in accordance with some embodiments.

6. The computing platform of claim 1, in which the error injection table structure comprises a table defining error injection status codes returned from GET COMMAND STATUS in accordance with an ACPI implementation.

7. The computing platform of claim 1, in which the error injection table structure comprises table listing error type codes returned from GET_ERROR TYPE in accordance with an ACPI implementation.

8. The computing platform of claim 7, in which the error injection table structure comprises a table showing a SET_ERROR_TYPE_WITH_ADDRESS data structure.

9. The computing platform claim 1, in which an OS is to inject an error through the PPM interface by sending a command through the PPM interface to inject the error and then triggering the error as a separate action.

10. An apparatus, comprising:

a first memory storage device having instructions operating system (OS) including OS PPM components for a PPM interface;

a second memory storage device having instructions for a firmware boot program including firmware PPM components for the PPM interface, the OS and firmware PPM instructions, when executed, to establish the PPM interface between the OS and platform hardware, the interface including an error injection data structure to enable the OS to cause an error into a desired hardware component.

11. The computing platform of claim 10, in which the error injection data structure is an EINJ structure in accordance with an ACPI specification.

12. An apparatus, comprising:

a computer platform having firmware including ACPI components to build an error injection data table (EINJ) structure for an ACPI interface.

13. The apparatus of claim 12, in which the computing platform is one of a tablet, a smart-phone, and a server computer.