VERTICAL TYPE SEMICONDUCTOR DEVICES INCLUDING OXIDATION TARGET LAYERS

• US 20140054676A1
• Filed: 08/20/2013
• Published: 02/27/2014
• Est. Priority Date: 08/27/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Byong-Hyun Jang, Jun-Kyu Yang, Phil-Ouk Nam
• Inventors: Yang, Jun-Kyu, Ahn, Jae-Young, Nam, Phil-Ouk, Jang, Byong-Hyun, Hwang, Ki-Hyun
• Granted Patent: US 8,987,805 B2
• Time in Patent Office: Days
• US Class Current: 257/324
• CPC Class Codes: H01L 29/7889 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

A vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps. Horizontal wordline structures can be conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, so that the horizontal wordline structures can be vertically thinner across the first vertical gaps than across the second vertical gaps.

Claims

1. A vertical type semiconductor device comprising:

a pillar structure including a semiconductor pattern and a channel pattern protruding in a first direction, the first direction being a vertical direction relative to an upper surface of a substrate;

first word line structures horizontally extending to surround the pillar structure at a facing portion relative to the channel pattern, the first word line structures including a blocking dielectric layer pattern and a metal pattern wherein, a height of the first word line structures being enlarged at a portion making contact with the pillar structure; and

a first insulating structure surrounding the pillar structure between the first word line structures in the first direction, the first insulating structure including a first portion having a relatively smaller height and making contact with the pillar structure and a second portion horizontally extended to a side direction of the first portion.

2. The semiconductor device of claim 1, wherein the first portion of the first insulating structure includes a polysilicon of which surface is covered with an oxide, or silicon nitride of which surface is covered with an oxide.

3. The semiconductor device of claim 1, wherein the first portion of the first insulating structure includes a thermal oxidation layer pattern.

4. The semiconductor device of claim 1, wherein the second portion of the first insulating layer structure includes silicon oxide formed using chemical vapor deposition.

5. The semiconductor device of claim 1, further comprising a second word line structure surrounding the pillar structure at a portion facing the semiconductor pattern.

6. The semiconductor device of claim 5, wherein the semiconductor pattern includes a groove shaped side wall portion making contact with the second word line structure, and the second word line structure includes a protruding shape at the groove shaped side wall and making contact with the semiconductor pattern.

7. The semiconductor device of claim 1, wherein the pillar structure includes layers of a first blocking dielectric layer including a tunnel insulating layer, a charge storing layer and silicon oxide layer surrounding an outer wall of the channel pattern.

8. The semiconductor device of claim 1, wherein the pillar structure includes a tunnel insulating layer and a charge storing layer stacked one by one to surround an outer wall of the channel pattern.

9. The semiconductor device of claim 1, wherein a blocking dielectric layer included in the first word line structure includes a metal oxide.

10-18. -18. (canceled)

19. A vertical type semiconductor device comprising:

a vertical pillar structure including a channel pattern with an outer wall;

horizontal insulating structures vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and second vertical gaps therebetween at the outer wall, the second vertical gaps being wider than the first vertical gaps; and

horizontal wordline structures conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, the horizontal wordline structures being vertically thinner across the first vertical gaps than across the second vertical gaps.

20. The device of claim 19 wherein the horizontal insulating structures further comprise:

respective oxidation target layers on the outer wall of the channel pattern providing upper and lower vertical boundaries of the second vertical gaps.

21. The device of claim 19 wherein upper and lower vertical boundaries of the second vertical gaps are recessed relative to upper and lower vertical boundaries of the horizontal insulating structures at the first locations.

22. The device of claim 19 wherein the oxidation target layers further comprise a layer including oxidized upper and lower portions providing the upper and lower vertical boundaries, respectively.

23. The device of claim 22 wherein the layer comprises a polysilicon layer and the oxidized upper and lower portions comprise upper and lower silicon oxide portions of the polysilicon layer.

24. The device of claim 19 wherein the horizontal insulating structures further comprise:

respective silicon nitride layers on the outer wall of the channel pattern providing upper and lower vertical boundaries of the second vertical gaps.

25. The device of claim 19 wherein the outer wall comprises a first blocking dielectric layer contacting the horizontal insulating structures and contacting the horizontal wordline structures.

26. The device of claim 19 wherein the vertical pillar structure further comprises a groove in an outer surface thereof below a lower boundary of the channel pattern.

27. The device of claim 26 wherein the horizontal wordline structures comprise first horizontal wordline structures, the device further comprising:

at least one second horizontal wordline structure vertically spaced apart from the first horizontal wordline structures, and conformally protruding into the groove in the outer surface of the vertical pillar structure.

28. The device of claim 25 wherein horizontal wordline structures each comprise a metal pattern and a second blocking dielectric layer between the first blocking dielectric layer and the metal pattern.