ALIGNED GATE-ALL-AROUND STRUCTURE

• US 20140054724A1
• Filed: 08/24/2012
• Published: 02/27/2014
• Est. Priority Date: 08/24/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kuo-Cheng, Colinge, Jean-Pierre, Wu, Zhiqiang
• Granted Patent: US 9,006,829 B2
• Time in Patent Office: Days
• US Class Current: 257/410
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Among other things, a semiconductor device comprising an aligned gate and a method for forming the semiconductor device are provided. The semiconductor device comprises a gate formed according to a multi-gate structure, such as a gate-all-around structure. A first gate portion of the gate is formed above a first channel of the semiconductor device. A second gate portion of the gate is formed below the first channel, and is aligned with the first gate portion. In an example of forming the gate, a cavity is etched within a semiconductor layer formed above a substrate. A dielectric layer is formed around at least some of the cavity to define a region of the cavity within which the second gate portion is to be formed in a self-aligned manner with the first gate portion. In this way, the semiconductor device comprises a first gate portion aligned with a second gate portion.

Claims

1. A semiconductor device, comprising:

a gate;

a semiconductor layer disposed between a substrate, upon which the semiconductor device is formed, and at least one of;

at least some of a first channel of the semiconductor device;

at least some of a source region of the semiconductor device;

or

at least some of a drain region of the semiconductor device;

a dielectric layer disposed between the substrate and at least one of;

at least some of the first channel;

at least some of the source region;

or

at least some of the drain region;

a first gate portion of the gate disposed above the first channel; and

a second gate portion of the gate disposed between the substrate and the first channel and aligned with the first gate portion.

2. The semiconductor device of claim 1, the gate comprising a gate-all-around structure.

3. The semiconductor device of claim 1, the semiconductor device configured as a FinFET, tri-gate or multi-gate device.

4. The semiconductor device of claim 1, the second gate portion disposed between a first dielectric portion of the dielectric layer and a second dielectric portion of the dialectic layer.

5. The semiconductor device of claim 4, the second gate portion disposed between the first channel and a third dielectric portion of the dialectic layer.

6. The semiconductor device of claim 1, at least one of the first channel, the source region, or the drain region formed within a semiconductor fin of the semiconductor device.

7. The semiconductor device of claim 1, the semiconductor layer comprising silicon germanium.

8. The semiconductor device of claim 1, the dielectric layer comprising silicon germanium oxide.

9. The semiconductor device of claim 1, comprising at least one of:

a high k dielectric material disposed between the second gate portion of the gate and the substrate;

or

a high k dielectric material disposed between the second gate portion of the gate and the first channel.

10. The semiconductor device of claim 1, comprising:

a second channel disposed between the second gate portion of the gate and the substrate; and

a third gate portion of the gate disposed between the second channel and the substrate, the third gate portion aligned with the first gate portion and the second gate portion of the gate.

11. A semiconductor device, comprising:

a gate-all-around structure;

a semiconductor layer disposed between a first channel of the semiconductor device and a substrate upon which the semiconductor device is formed;

a dielectric layer disposed between the semiconductor layer and the first channel, the dielectric layer comprising an oxidized portion of the semiconductor layer;

a second gate portion of the gate-all-round structure disposed between the dielectric layer and the first channel and aligned with a first gate portion of the gate-all-around structure above the first channel;

a second channel disposed between the second gate portion of the gate-all-round structure and the dielectric layer; and

a third gate portion of the gate-all-round structure disposed between the second channel and the dielectric layer, the third gate portion aligned with the first gate portion and the second gate portion of the gate-all-around structure.

12. The semiconductor device of claim 11, the second gate portion disposed within a cavity within the dielectric layer.

14. The semiconductor device of claim 11, the semiconductor layer comprising silicon germanium, and the dielectric layer comprising silicon germanium oxide.

15. The semiconductor device of claim 11, comprising at least one of:

a high k dielectric material disposed between the second gate portion and the first channel;

a high k dielectric material disposed between the second gate portion and the second channel;

a high k dielectric material disposed between the third gate portion and the second channel;

or

a high k dielectric material disposed between the third gate portion and the dielectric layer.

16. A method for fabricating a semiconductor device, comprising:

forming a semiconductor layer between a first channel of the semiconductor device and a substrate upon which the semiconductor device is formed;

forming a cavity within the semiconductor layer between the first channel and the substrate;

exposing the semiconductor layer to oxygen to form a dielectric layer around at least some of the cavity, the dielectric layer extending under at least one of;

at least some of the first channel of the semiconductor device;

at least some of a source region of the semiconductor device;

or

at least some of a drain region of the semiconductor device; and

forming a second gate portion of a gate of the semiconductor device within at least some of the cavity, the second gate portion disposed between the substrate and the first channel, the second gate portion aligned with a first gate portion of the gate above the first channel.

13. The semiconductor device of claim 16, the dielectric layer extending under at least one of:

at least some of the first channel of the semiconductor device;

at least some of the second channel of the semiconductor device;

at least some of a source region of the semiconductor device;

or

at least some of a drain region of the semiconductor device.

17. The method of claim 16, the semiconductor layer comprising silicon germanium.

18. The method of claim 16, comprising:

forming the gate as a gate-all-around structure.

19. The method of claim 16, comprising:

forming a second channel disposed between the second gate portion of the gate and the substrate; and

forming a third gate portion of the gate disposed between the second channel and the substrate, the third gate portion aligned with the first and second gate portions of the gate.

20. The method of claim 16, the forming a second gate portion comprising:

forming the second gate portion between a first dielectric portion of the dielectric layer and a second dielectric portion of the dialectic layer.