SEMICONDUCTOR DEVICES INCLUDING METAL-SILICON-NITRIDE PATTERNS AND METHODS OF FORMING THE SAME

• US 20140054775A1
• Filed: 03/12/2013
• Published: 02/27/2014
• Est. Priority Date: 08/27/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Mansug Kang, Seonghwee Cheong
• Inventors: Kang, Mansug, Kim, Taekjung, Kong, Myung-Ho, Park, Heesook, Park, Youngwook, Cheong, Seonghwee
• Granted Patent: US 9,099,473 B2
• Time in Patent Office: Days
• US Class Current: 257/751
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53266 Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53271 containing semiconductor material, e.g. polysilicon
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H01L 29/0642 Isolation within the component, i.e. internal isolation
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/318 the storage electrode having multiple segments
• CPC Class Codes: H10B 12/482 Bit lines
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type

Abstract

A semiconductor memory device can include a first conductive line crossing over a field isolation region and crossing over an active region of the device, where the first conductive line can include a first conductive pattern being doped, a second conductive pattern, and a metal-silicon-nitride pattern between the first and second conductive patterns and can be configured to provide a contact at a lower boundary of the metal-silicon-nitride pattern with the first conductive pattern and configured to provide a diffusion barrier at an upper boundary of the metal-silicon-nitride pattern with the second conductive pattern.

Claims

1. A semiconductor memory device comprising:

a first conductive line crossing over a field isolation region and crossing over an active region of the device, the first conductive line including a first conductive pattern being doped, a second conductive pattern, and a metal-silicon-nitride pattern between the first and second conductive patterns and configured to provide a contact at a lower boundary of the metal-silicon-nitride pattern with the first conductive pattern and configured to provide a diffusion barrier at an upper boundary of the metal-silicon-nitride pattern with the second conductive pattern.

2. The device of claim 1 wherein the first conductive line crosses over the field isolation region and over the active region in a cell array region of the device, the device further comprising:

a second conductive line crossing over a field isolation region and over an active region in a peripheral region of the device, the second conductive line including a third conductive pattern being doped, and a fourth second conductive pattern, and a metal-silicon-nitride pattern between the third and fourth conductive patterns and configured to provide a contact at a lower boundary of the metal-silicon-nitride pattern with the third conductive pattern and a diffusion barrier at an upper boundary of the metal-silicon-nitride pattern with the fourth conductive pattern in the peripheral region.

3. The device of claim 2 wherein the first conductive line comprises a bit line and the second conductive line comprises a peripheral gate structure.

4. The device of claim 1 wherein the metal-silicon-nitride pattern includes a metal silicide comprising the contact.

5. The device of claim 4 wherein the contact comprises an ohmic contact.

6. The device of claim 1 wherein the metal-silicon-nitride pattern comprises a total thickness of about 30 Angstroms to about 70 Angstroms and the first conductive pattern comprises a total thickness of about 200 Angstroms to about 400 Angstroms.

7. The device of claim 6 wherein the first conductive line comprises a total thickness less than about 800 Angstroms.

8. The device of claim 7 wherein the total thickness of the first conductive line is greater than about 550 Angstroms.

9. The device of claim 8 wherein the total thickness of the first conductive pattern is about 350 Angstroms.

10. The device of claim 9 wherein the second conductive pattern comprises a total thickness of about 300 Angstroms.

11. The device of claim 1 wherein the metal-silicon-nitride pattern comprises a total thickness of about 10% to about 25% of a total thickness of the first conductive pattern.

12. The device of claim 1 wherein a total thickness of the metal-silicon-nitride pattern is less than a total thickness of the second conductive pattern, which is less than a total thickness of the first conductive pattern.

13. The device of claim 1 wherein the metal-silicon-nitride pattern comprises a silicon concentration of at least about 10 atm % measured over a total thickness of the metal-silicon-nitride pattern.

14. The device of claim 13 wherein the silicon concentration comprises a first concentration of about 10 atm % to about 30 atm % measured adjacent the upper boundary and comprises a second concentration of about 30 atm % to about 50 atm % measured adjacent the lower boundary.

15. The device of claim 14 wherein the silicon concentration changes from the first concentration to the second concentration throughout the metal-silicon-nitride pattern.

16. The device of claim 1 wherein the metal-silicon-nitride pattern comprises silicon-nitride layers interspersed with metal-nitride layers.

17. The device of claim 1 wherein the metal-silicon-nitride pattern comprises a TiSiN pattern.

18. The device of claim 17 wherein the TiSiN pattern comprises SiN layers interspersed with TiN layers.

19. The device of claim 1 wherein a crystal grain size included in the metal-silicon-nitride pattern comprises about 10% or less of a crystal grain size included in the second conductive pattern.

20. The device of claim 1 wherein a crystal structure in the metal-silicon-nitride pattern comprises a fine crystal structure including fine metal-nitride sub-grains having spaces therebetween and silicon-nitride in the spaces.

21. The device of claim 1 wherein the semiconductor memory device comprises a DRAM and the first conductive line comprises a bit line included in a BCAT in a cell array region of the DRAM.

22. The device of claim 1 wherein the semiconductor memory device comprises an MRAM.

23. The device of claim 1 wherein the semiconductor memory device comprises a vertical channel DRAM.

24-89. -89. (canceled)