Multi-Level Vertical Plug Formation With Stop Layers of Increasing Thicknesses

• US 20140054789A1
• Filed: 08/23/2012
• Published: 02/27/2014
• Est. Priority Date: 08/23/2012
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lee, Guanru, Chiu, Chiajung
• Granted Patent: US 8,736,069 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A method is provided for use with an IC device including a stack including a plurality of conductive layers interleaved with a plurality of dielectric layers, for forming interlayer connectors extending from a connector surface to respective conductive layers. The method forms landing areas on the plurality of conductive layers in the stack. The landing areas are without overlying conductive layers in the stack. The method forms etch stop layers over corresponding landing areas. The etch stop layers have thicknesses that correlate with depths of the corresponding landing areas. The method fills over the landing areas and the etch stop layers with a dielectric fill material. Using a patterned etching process, the method forms a plurality of vias extending through the dielectric fill material and the etch stop layers to the landing areas in the plurality of conductive layers.

Claims

1. A method for use with an integrated circuit device including a stack including a plurality of conductive layers interleaved with a plurality of dielectric layers within a pit formed within a substrate such that an uppermost one of the conductive layers is below a top surface of the substrate, for forming interlayer connectors extending from a connector surface to respective ones of the plurality of conductive layers, the method comprising:

forming landing areas on the plurality of conductive layers in the stack, the landing areas without overlying conductive layers in the stack;

forming etch stop layers over corresponding landing areas, the etch stop layers having thicknesses that correlate with depths of the corresponding landing areas;

filling over the landing areas and the etch stop layers with a dielectric fill material;

using a patterned etching process to form a plurality of vias extending through the dielectric fill material and the etch stop layers to the landing areas in the plurality of conductive layers; and

forming an isolation region extending into the substrate separating the stack from an array periphery region.

2. The method of claim 1, the patterned etching process including first opening down to the etch stop layers, and second breaking through the etch stop layers to expose the landing areas.

3. The method of claim 1, wherein said forming landing areas includes removing portions of the conductive layers and the dielectric layers in the stack.

4. The method of claim 3, wherein said removing portions includes using a set of N etch masks with 2^N-1 being less than W and 2^N being greater than or equal to W, the etch masks having mask regions and spaced apart open etch regions corresponding to selected landing areas, wherein the W is the number of total conductive layers;

for each etch mask n, where n goes from 1 to N, etching 2^n-1 conductive layers over up to half of the landing areas, so that the landing areas on the plurality of conductive layers are exposed with different combinations of the etch masks; and

said forming etch stop layers includes, after etching using at least two of the etch masks, forming a layer of etch stop material over the landing areas before etching using another of the etch masks.

5. The method of claim 4, including:

said forming etch stop layers includes, after etching using each of the N etch masks, forming a layer of etch stop material over the landing areas before etching using another of the etch masks.

6. The method of claim 1, including forming interlayer connectors by filling the vias with conductive material up to the connector surface.

7. The method of claim 1, including forming patterned conductor lines on top of the connector surface and connected to respective interlayer connectors.

8. An integrated circuit comprising a plurality of conductive layers and a plurality of interlayer connectors made as set forth in claim 6.

9. The integrated circuit of claim 8, wherein the plurality of conductive layers are connected to corresponding planes of a 3D memory array.

10. An integrated circuit including a multi-level vertical plug formation with stop layers of increasing thicknesses, comprising:

a substrate within which a pit is formed;

a stack including a plurality of conductive layers interleaved with a plurality of dielectric layers within the pit such that an uppermost one of the conductive layers is below a top surface of the substrate;

landing areas on the plurality of conductive layers in the stack, the landing areas without overlying conductive layers in the stack;

etch stop layers over corresponding landing areas, the etch stop layers having thicknesses that correlate with depths of the corresponding landing areas;

a plurality of vias extending through the etch stop layers to the landing areas in the plurality of conductive layers;

interlayer connectors connected to respective conductive layers in the stack through the plurality of vias; and

an isolation region extending into the substrate separating the stack from an array periphery region.

11. The integrated circuit of claim 10, wherein the interlayer connectors have depths increasing from the greatest depth at the first interlayer connector to the shallowest depth at the last interlayer connector.

12. The integrated circuit of claim 10, further comprising patterned conductor lines on top of the connector surface and connected to respective interlayer connectors.

13. The integrated circuit of claim 10, further comprising dielectric formations in a plurality of dielectric formations interleaved with the interlayer connectors.

14. The integrated circuit of claim 13, wherein the dielectric formations have depths increasing from the greatest depth at the first dielectric formation to the shallowest depth at the last dielectric formation.

15. The integrated circuit of claim 13, wherein the dielectric formations are separated from dielectric layers in the plurality of dielectric layers by the etch stop layers.

16. The integrated circuit of claim 10, wherein:

the plurality of etch stop layers includes N etch stop layers corresponding to N interlayer connectors;

for each etch stop layer n, where n goes from 1 to m1, the etch stop layer n has a first thickness approximately equal to the thickness of etch stop layer 1;

for each etch stop layer n, where n goes from (m1+1) to m2, the etch stop layer n has a second thickness approximately equal to twice the thickness of etch stop layer 1; and

for each etch stop layer n, where n goes from (m2+1) to N, the etch stop layer n has a third thickness approximately equal to three times the thickness of etch stop layer 1;

wherein m1 is greater than 1 and less than m2, and m2 is greater than m1 and less than N.

17. The integrated circuit of claim 10, wherein:

the plurality of etch stop layers includes N etch stop layers corresponding to N interlayer connectors;

for each etch stop layer n, where n goes from 1 to m, the etch stop layer n has a first thickness approximately equal to the thickness of etch stop layer 1; and

for each etch stop layer n, where n goes from (m+1) to N, the etch stop layer n has a second thickness approximately equal to twice the thickness of etch stop layer 1;

wherein m is greater than 1 and less than N.

18. The integrated circuit of claim 10, wherein:

the plurality of etch stop layers includes N etch stop layers corresponding to N interlayer connectors;

for each etch stop layer n, where n goes from 1 to (N−

1), the etch stop layer n has a thickness approximately equal to n times the thickness of etch stop layer 1; and

etch stop layer N has a thickness approximately equal to (N−

1) times the thickness of etch stop layer 1.

19. A method for use with an integrated circuit device including a stack including a plurality of conductive layers interleaved with a plurality of dielectric layers within a pit formed within a substrate such that an uppermost one of the conductive layers is below a top surface of the substrate, for forming interlayer connectors extending from a connector surface to respective ones of the plurality of conductive layers, the method comprising:

forming landing areas on the plurality of conductive layers in the stack, the landing areas without overlying conductive layers in the stack;

forming etch stop layers over corresponding landing areas, the etch stop layers having thicknesses that correlate with depths of the corresponding landing areas;

filling over the landing areas and the etch stop layers with a dielectric fill material;

using a patterned etching process to form a plurality of vias extending through the dielectric fill material and the etch stop layers to the landing areas in the plurality of conductive layers;

forming an isolation region extending into the substrate separating the stack from an array periphery region;

forming interlayer connectors by filling the vias with conductive material up to a connector surface; and

forming patterned conductor lines on top of the connector surface and connected to respective interlayer connectors;

wherein said forming landing areas includes removing portions of the conductive layers and the dielectric layers in the stack; and

wherein said removing portions includes using a set of N etch masks with 2^N-1 being less than W and 2^N being greater than or equal to W, the etch masks having mask regions and spaced apart open etch regions corresponding to selected landing areas, wherein the W is the number of total conductive layers;

for each etch mask n, where n goes from 1 to N, etching 2^n-1 conductive layers over up to half of the landing areas, so that the landing areas on the plurality of conductive layers are exposed with different combinations of the etch masks; and

said forming etch stop layers includes, after etching using at least two of the etch masks, forming a layer of etch stop material over the landing areas before etching using another of the etch masks.

20. The method of claim 19, including after said filling the vias with conductive material, planarizing dielectric fill material to form the connector surface.