MEMORY CELL AND MEMORY

• US 20140056050A1
• Filed: 08/27/2013
• Published: 02/27/2014
• Est. Priority Date: 08/27/2012
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: Hua Chen, Hwong-Kwo Lin, Jun Yang, Ju Shen, Yong Li
• Inventors: YANG, Jun, LIN, Hwong-Kwo, CHEN, Hua, LI, Yong, SHEN, Ju
• Granted Patent: US 9,496,047 B2
• Time in Patent Office: Days
• US Class Current: 365/103
• CPC Class Codes: G11C 17/08 using semiconductor devices, e.g. bipolar elements G11C17/06, G11C17/14 take precedence
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

In various embodiments, a memory cell and a memory are provided. The memory cell comprises a Static Random Access Memory (SRAM) cell including a reset-set (RS) flip-flop and a Read Only Memory (ROM) cell being connected (or coupled) to the SRAM cell to set logic states of internal latch nodes of the RS flip-flop when the ROM cell is triggered. The size of the memory cells proposed in an embodiment of the invention is much smaller than the sum of the size of ROM cells and the size of SRAM cells with the capacity of the memory cells same as the sum of the capacity of the ROM cells and the capacity of the SRAM cells.

Claims

1. A memory cell comprising:

a Static Random Access Memory (SRAM) cell comprising a reset-set (RS) flip-flop; and

a Read Only Memory (ROM) cell coupled to the SRAM cell to set logic states of internal latch nodes of the RS flip-flop when the ROM cell is triggered.

2. The memory cell of claim 1, wherein the ROM cell comprises a transistor that couples one of the internal latch nodes of the RS flip-flop with ground and a gate of that is used to receive a triggering signal from a triggering word line.

3. The memory cell of claim 2, wherein the transistor is an NMOS transistor.

4. The memory cell of claim 1, wherein the ROM cell comprises:

a first transistor that couples a first internal latch node of the RS flip-flop with ground and a gate that is used to receive a triggering signal from a triggering word line; and

a second transistor, wherein its source is coupled to the ground and its drain is decoupled from a second internal latch node of the RS flip-flop, and its gate is used to receive the triggering signal from the triggering word line.

5. The memory cell of claim 4, wherein the first transistor and the second transistor are NMOS transistors.

6. The memory cell of claim 1, wherein the ROM cell comprises:

a first transistor that couples a first internal latch node of the RS flip-flop with ground and a gate that is used to receive a triggering signal from a triggering word line; and

a second transistor that couples a second internal latch node of the RS flip-flop with the ground and a gate that is coupled to the ground.

7. The memory cell of claim 6, wherein the first transistor and the second transistor are NMOS transistors.

8. The memory cell of claim 6, wherein the first transistor and the first internal latch node of the RS flip-flop and the second transistor and the second internal latch node of the RS flip-flop are coupled through a metal layer.

9. The memory cell of claim 1, wherein the ROM cell is coupled to the SRAM cell through a diffusion, a contact, or a metal layer.

10. The memory cell of claim 1, wherein the SRAM cell further comprises pass transistors, which are used to couple the internal latch nodes of the RS flip-flop with bit lines, the gates of the pass transistors are coupled to a word line.

11. The memory cell of claim 1, wherein the RS flip-flop comprises two amplifiers that are reversely coupled.

12. The memory cell of claim 1, wherein the SRAM cell is a Random Access Memory (RAM) cell comprising 6 transistors.

13. A memory array comprising:

multiple memory cells, each memory cell comprising;

a Static Random Access Memory (SRAM) cell comprising a reset-set (RS) flip-flop; and

a Read Only Memory (ROM) cell coupled to the SRAM cell to set logic states of internal latch nodes of the RS flip-flop when the ROM cell is triggered;

multiple bit lines, each bit line coupled to memory cells in a respective column;

multiple word lines, each word line coupled to memory cells in a respective row; and

multiple triggering word lines, each triggering word line coupled to memory cells in a respective row to trigger the ROM cells of the memory cells in the respective row.

14. The memory of claim 13, wherein said each ROM cell comprises a transistor that couples one of the internal latch nodes of the RS flip-flop with ground and a gate that is used to receive a triggering signal from the triggering word line.

15. The memory of claim 13, wherein said each ROM cell comprises:

a first transistor that couples a first internal latch node of the RS flip-flop with ground and a gate of that is used to receive a triggering signal from the triggering word line; and

a second transistor, wherein its source is coupled to the ground and its drain is decoupled from a second internal latch node of the RS flip-flop, and its gate is used to receive the triggering signal from the triggering word line.

16. The memory of claim 13, wherein said each ROM cell includes:

a first transistor that couples a first internal latch node of the RS flip-flop with ground and a gate that is used to receive a triggering signal from the triggering word line; and

a second transistor that couples a second internal latch node of the RS flip-flop with the ground and a gate that is coupled to the ground.

17. The memory of claim 13, wherein said each ROM cell is coupled to its corresponding SRAM cell through a diffusion, a contact, or a metal layer.

18. The memory of claim 13, wherein the multiple triggering word lines share a public triggering signal.

19. The memory of claim 13, wherein each of the multiple triggering word lines receives a respective triggering signal.

20. The memory of claim 19, further comprising a read-only address decoding circuit that is used to select an expected triggering word line among the multiple triggering word lines.