Symmetrical Differential Sensing Method and System for STT MRAM

• US 20140056059A1
• Filed: 08/23/2012
• Published: 02/27/2014
• Est. Priority Date: 08/23/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Mueller, David, Allers, Wolf, Jefremow, Mihail
• Granted Patent: US 9,076,540 B2
• Time in Patent Office: Days
• US Class Current: 365/158
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In one example, a system for reading a memory cell includes a sense path and an inverse path. A reference current is provided through the sense path and is sampled via a first sampling element in the sense path, and a cell current from the memory cell is provided through the inverse sense path and is sampled via a second sampling element in the inverse sense path. Subsequently, the memory cell is disconnected from the inverse sense path, the cell current is provided through the sense path, the reference source is disconnected from the sense path, and the reference current is provided through the inverse sense path. The output levels are then determined by the cell and reference currents working against the sampled reference and sampled cell currents.

Claims

1. A method for reading a memory cell, comprising:

providing a first sampling element for sampling a reference current in a sense path;

providing a second sampling element for sampling a cell current from the memory cell;

measuring the cell current from the memory cell using the first sampling element; and

measuring the reference current using the second sampling element.

2. The method of claim 1, further comprising of providing a reference source which provides the reference current through the first sampling element.

3. The method of claim 1, wherein the first sampling element comprises a diode connected MOS transistor.

4. The method of claim 1, wherein the second sampling element comprises a diode connected MOS transistor.

5. The method of claim 1, wherein the reference current is sampled by a voltage across at least a portion of the first sampling element on a first capacitance, and the cell current is sampled by a voltage across at least a portion of the second sampling element on a second capacitance.

6. The method of claim 1, further comprising providing an inverse sense path for the memory cell when sampling the cell current, wherein the inverse sense path for the memory cell is a different path than the sense path.

7. The method of claim 6, wherein providing the inverse sense path through the second sampling element for the cell current occurs around the same time as providing the sense path through the first sampling element for the reference current.

8. The method of claim 7, further comprising switching the memory cell from the inverse sense path to the sense path through the first sampling element after sampling the cell reference current and the cell current.

9. The method of claim 8, wherein the reference current is sampled by a voltage across at least a portion of the first sampling element on a first capacitance, and the cell current is sampled by a voltage across at least a portion of the second sampling element on a second capacitance, and further comprising disconnecting the first capacitance and the second capacitance from the first sampling element and the second sampling element, respectively.

10. The method of claim 8, wherein a first node associated with the first sampling element comprises a first output and a second node associated with the second sampling element comprises a second output, and wherein the first and second outputs of the sensing system both carry the difference signal with opposite sign.

11. The method of claim 1, wherein the memory cell comprises an STT MRAM.

12. A system for reading a memory cell, comprising:

a reference source configured to provide a reference current for the memory cell;

a first sampling element selectively coupled to the reference source and configured to sample and hold the reference current; and

a second sampling element selectively coupled to the memory cell and configured to sample and hold a cell current from the memory cell;

wherein the reference current and the memory cell current are subsequently switched via a switching circuit such that the reference current flows through the second sampling element and the cell current flows through the first sampling element.

13. The system of claim 12, wherein the memory cell comprises an STT MRAM.

14. The system of claim 12, wherein the first sampling element and the second sampling element each comprise a diode connected sampling transistor.

15. The system of claim 12, wherein the reference current is sampled by a voltage across the first sampling element on a first capacitance.

16. The system of claim 12, wherein the cell current is sampled by a voltage across the second sampling element on a second capacitance.

17. The system of claim 12, wherein the reference current flows through the first sampling element at substantially the same time as the cell current flows through the second sampling element.

18. The system of claim 17, wherein in one switching configuration of the switching circuit the reference current flows through the second sampling element and the cell current flows through the first sampling element.

19. The system of claim 18, wherein the reference current is sampled by a voltage across the first sampling element on a first capacitance, wherein the cell current is sampled by a voltage across the second sampling element on a second capacitance, and wherein the first and second capacitances are disconnected from the inputs when the reference current flows through the second sampling element and the cell current flows through the first sampling element.

20. A system for sensing a memory cell, the memory cell having an associated reference source for providing a reference current, comprising:

a sense path configured to be coupled alternately to either the reference source or the memory cell via a switching circuit; and

an inverse sense path configured to be coupled alternately to either the reference source or the memory cell via the switching circuit;

wherein the memory cell is switched via the switching circuit from the inverse sense path to the sense path after the reference current has flowed through the sense path.

21. The system of claim 20, wherein the sense path comprises a first diode connected sampling transistor configured to sample and hold the reference current.

22. The system of claim 20, wherein the inverse sense path comprises a second diode connected sampling transistor configured to sample and hold the cell current.

23. The system of claim 20, wherein the memory cell is coupled to the inverse sense path via the switching circuit at substantially the same time that the reference current flows through the sense path.

24. The system of claim 21, wherein the reference current is sampled by a voltage across the first sampling transistor on a first capacitance.

25. The system of claim 23, wherein the memory cell is disconnected from the inverse sense path and then provides a cell current that flows through the sense path via the switching circuit.

26. The system of claim 23, wherein the reference source is disconnected from the sense path and then provides the reference current that flows through the inverse sense path via the switching circuit.

27. The system of claim 24, wherein the first capacitance is disconnected from the first sampling transistor via the switching circuit after the first sampling transistor has sampled the reference current.

28. The system of claim 20, wherein a first node associated with the first sampling element comprises a first output and a second node associated with the second sampling element comprises a second output, and wherein output levels at the first and second outputs of the system both carry the difference signal with opposite sign.

29. The system of claim 20, wherein the memory cell comprises an STT MRAM.

30. A method for reading a memory cell, comprising:

providing a sense path for the memory cell and an associated reference source;

providing a reference current through the sense path;

providing an inverse sense path for the memory cell at substantially the same time that the reference current is provided through the sense path;

disconnecting the memory cell from the inverse sense path;

providing a cell current from the memory cell through the sense path; and

providing the reference current through the inverse sense path.

31. The method of claim 30, wherein the memory cell comprises an STT MRAM.

32. The method of claim 30, wherein the sense path comprises a first sampling element and the inverse sense path comprises a second sampling element.

33. The method of claim 32, wherein the first and second sampling elements each comprise diode connected MOS transistors.

34. The method of claim 30, wherein the reference current and the cell current are sampled by voltages across the gates of the first and second sampling elements, respectively, on a first capacitance and a second capacitance, respectively.

35. The method of claim 34, further comprising measuring the cell current from the memory cell using the first sampling element.

36. The method of claim 30, wherein a first node associated with the first sampling element comprises a first output and a second node associated with the second sampling element comprises a second output, and wherein the first and second outputs of the sensing system both carry the difference signal with opposite sign.