High Precision Timer in CPU Cluster

• US 20140056319A1
• Filed: 03/13/2013
• Published: 02/27/2014
• Est. Priority Date: 08/21/2012
• Status: Active Grant

• Current Assignee: SMART Embedded Computing, Inc. (Smart Global Holdings Incorporated)
• Original Assignee: Emerson Network Power Embedded Computing Inc.
• Inventors: HELLWIG, Mathias
• Granted Patent: US 10,110,367 B2
• Time in Patent Office: Days
• US Class Current: 370/503
• CPC Class Codes: H04J 3/0667 Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays arrangements for monitoring round trip delays in packet switching networks H04L43/0864
• CPC Class Codes: H04J 3/0688 Change of the master or reference, e.g. take-over or failure of the master
• CPC Class Codes: H04J 3/0697 Synchronisation in a packet node
• CPC Class Codes: H04L 7/00 Arrangements for synchronising receiver with transmitter synchronisation of generators of electric oscillations or pulses H03L7/00

Abstract

A system includes a first node that generates a first clock signal having a frequency, generates a plurality of data packets, modifies the data packets to include data indicative of time and phase information associated with the first node, and transmits the data packets. A second node receives the plurality of data packets and the first clock signal, determines the time and phase information based on the plurality of data packets, determines the frequency based on the first clock signal, and generates at least one of a second clock signal and a local time based on the time and phase information and the frequency of the first clock signal.

Claims

1. A system, comprising:

a first node that generates a first clock signal having a frequency, generates a plurality of data packets, modifies the data packets to include data indicative of time and phase information associated with the first node, and transmits the data packets; and

a second node that receives the plurality of data packets and the first clock signal, determines the time and phase information based on the plurality of data packets, determines the frequency based on the first clock signal, and generates at least one of a second clock signal and a local time based on the time and phase information and the frequency of the first clock signal.

2. The system of claim 1, wherein the data indicative of time and phase information includes at least one timestamp.

3. The system of claim 1, wherein the first node is a master node and the second node is a slave node.

4. The system of claim 1, wherein the first node includes a switch module that modifies the data packets to include the data indicative of time and phase information and transmits the data packets.

5. The system of claim 4, wherein the switch module includes an Ethernet switch that operates according to IEEE 1588 protocol.

6. The system of claim 1, wherein the second node includes a packet synchronization module that determines the time and phase information.

7. The system of claim 6, wherein the packet synchronization module determines the time and phase information using a packet-based timing scheme according to IEEE 1588 protocol.

8. The system of claim 1, wherein the second node includes a slave clock generation module that generates the at least one of the second clock signal and the local time based on the time and phase information and the frequency of the first clock signal.

9. The system of claim 8, wherein the slave clock generation module implements a phase locked loop that locks the second clock signal to the first clock signal using the time and phase information and the frequency of the first clock signal.

10. The system of claim 1, further comprising a third node that generates a third clock signal, wherein:

the first node and the third node are master nodes;

the second node is a slave node; and

the second node selects between the first clock signal and the third clock signal.

11. The system of claim 1, wherein the first node and the second node are coupled to a backplane and communicate via the backplane.

12. A method, comprising:

at a first node,

generating a first clock signal having a frequency;

generating a plurality of data packets;

modifying the data packets to include data indicative of time and phase information associated with the first node; and

transmitting the data packets; and

at a second node,

receiving the plurality of data packets and the first clock signal;

determining the time and phase information based on the plurality of data packets;

determining the frequency based on the first clock signal; and

generating at least one of a second clock signal and a local time based on the time and phase information and the frequency of the first clock signal.

13. The method of claim 12, wherein the data indicative of time and phase information includes at least one timestamp.

14. The method of claim 12, wherein the first node is a master node and the second node is a slave node.

15. The method of claim 12, wherein modifying the data packets to include the data indicative of time and phase information includes modifying the data packets according to IEEE 1588 protocol.

16. The method of claim 12, wherein determining the time and phase information includes determining the time and phase information using a packet-based timing scheme according to IEEE 1588 protocol.

17. The method of claim 12, further comprising implementing a phase locked loop to lock the second clock signal to the first clock signal using the time and phase information and the frequency of the first clock signal.

18. The method of claim 12, further comprising:

at a third node, generating a third clock signal, wherein the first node and the third node are master nodes and the second node is a slave node; and

at the second node, selecting between the first clock signal and the third clock signal.

19. The method of claim 12, further comprising:

coupling the first node and the second node to a backplane; and

providing communication between the first node and the second node via the backplane.