ROW HAMMER REFRESH COMMAND

• US 20140059287A1
• Filed: 10/31/2013
• Published: 02/27/2014
• Est. Priority Date: 06/30/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Christopher Mozak, Kuljit Bains, Theodore Schoenborn, Zvika Greenfield
• Inventors: BAINS, Kuljit, HALBERT, Johm, MOZAK, Christopher, SCHOENBORN, Theodore, GREENFIELD, Zvika
• Granted Patent: US 9,117,544 B2
• Time in Patent Office: Days
• US Class Current: 711/106
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals

Abstract

A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

Claims

1. A system comprising:

a synchronous dynamic random access memory (SDRAM) device, the SDRAM device including;

a memory array to include one or more rows of memory cells;

a mode register to hold at least one mode register bit, the value of the at least one mode register bit to determine whether a targeted row refresh mode is enabled; and

targeted row refresh logic coupled with the memory array, the targeted row refresh logic capable of refreshing selected rows responsive, at least in part, to a targeted row refresh command; and

a memory controller coupled with the SDRAM device, the memory controller including detection logic to detect a targeted row refresh condition; and

command and control logic capable of issuing a command to transition the SDRAM device to a targeted row refresh mode, subsequent to detecting the targeted row refresh condition.

2. The system of claim 1, wherein the command to transition the SDRAM device to a targeted row refresh mode includes a Mode Register Set (MRS) command.

3. The system of claim 2, wherein the MRS command is an MRS2 command.

4. The system of claim 3, wherein the MRS2 command sets an MR2[A13] register to one.

5. The system of claim 2, wherein the command to transition the SDRAM device to a targeted row refresh mode includes at least one Activate (ACT) command.

6. The system of claim 5, wherein the ACT command is an ACT1 command.

7. The system of claim 1, wherein the SDRAM device is a DDR4 SDRAM device.

8. The system of claim 1, wherein the SDRAM device is a LPDDR4 SDRAM device.

9. A synchronous dynamic random access memory (SDRAM) device, the SDRAM device comprising:

a memory army to include one or more rows of memory cells;

a mode register to hold at least one mode register bit, the value of the at least one mode register bit to determine whether a targeted row refresh mode is enabled; and

targeted row refresh logic coupled with the memory array, the targeted row refresh logic capable of refreshing selected rows responsive, at least in part, to a targeted row refresh command.

10. The SDRAM device of claim 9, wherein the SDRAM device is a DDR4 SDRAM device.

11. The SDRAM device of claim 10, wherein the SDRAM device is a LPDDR4 SDRAM device.

12. A memory controller comprising:

a double data rate (DDR) interface to couple the memory controller to a DDR memory channel;

detection logic to detect a targeted row refresh condition; and

command and control logic capable of issuing a command to transition a synchronous dynamic random access memory (SDRAM) device to a targeted row refresh mode, subsequent to detecting the targeted row refresh condition.

13. The memory controller of claim 12, wherein the memory controller is integrated onto the same integrated circuit as a processor.

14. The memory controller of claim 12, wherein the SDRAM device is a DDR4 SDRAM device.

15. The memory controller of claim 12, wherein the SDRAM device is a LPDDR4 SDRAM device.