REDUCED LEVEL CELL MODE FOR NON-VOLATILE MEMORY

• US 20140059406A1
• Filed: 09/02/2013
• Published: 02/27/2014
• Est. Priority Date: 03/15/2010
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Fusion-IO Incorporated (Western Digital Corporation)
• Inventors: Hyun, Jea, Wood, Robert, Haynes, Ryan, Mosier, Charla, Lucky, Rick
• Granted Patent: US 9,245,653 B2
• Time in Patent Office: Days
• US Class Current: 714/773
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 2212/7209 Validity control, e.g. using flags, time stamps or sequence numbers
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

Apparatuses, systems, methods, and computer program products are disclosed for reduced level cell solid-state storage. A method includes determining that an erase block of a non-volatile storage device is to operate in a reduced level cell (RLC) mode. The non-volatile storage device may be configured to store at least three bits of data per storage cell. A method includes instructing the non-volatile storage device to program first and second pages of the erase block with data. A method includes instructing the non-volatile storage device to program a third page of the erase block with a predefined data pattern. Programming of a predefined data pattern may be configured to adjust which abodes of the erase block are available to represent stored user data values.

Claims

1. A method comprising:

determining that an erase block of a non-volatile storage device is to operate in a reduced level cell (RLC) mode, the non-volatile storage device configured to store at least three bits of data per storage cell;

instructing the non-volatile storage device to program a first page of the erase block with data;

instructing the non-volatile storage device to program a second page of the erase block with data; and

instructing the non-volatile storage device to program a third page of the erase block with a predefined data pattern, the programming of the predefined data pattern configured to adjust which abodes of the erase block are available to represent stored user data values, wherein the first, second, and third pages are associated with a same set of storage cells of the erase block.

2. The method of claim 1, further comprising performing an operation on the data of the first page and the data of the second page, wherein results of the operation comprise the predefined data pattern for the third page.

3. The method of claim 2, wherein the operation comprises an XNOR logical equality operation such that the available abodes of the erase block are not adjacent, one or more unavailable abodes being disposed between the available abodes.

4. The method of claim 2, further comprising buffering the data of the first page and the data of the second page prior to programming the first page and the second page of the erase block, the operation performed on the buffered data.

5. The method of claim 4, wherein the data of the first page and the data of the second page are buffered in one or more different erase blocks of the non-volatile storage device such that the data of the first page and the data of the second page may be programmed to the erase block after a restart event for the non-volatile storage device.

6. The method of claim 1, further comprising adjusting, for the RLC mode, one or more thresholds for the abodes of the TLC mode to provide one or more separation distances between the available abodes.

7. The method of claim 6, wherein the one or more thresholds are set to merge at least one of the available abodes with at least one abode unavailable to represent stored user data to provide the one or more separation distances.

8. The method of claim 6, wherein the one or more thresholds are set to move adjacent available abodes away from each other to provide the one or more separation distances.

9. The method of claim 1, further comprising maintaining a page of data in a different erase block of the non-volatile storage device, the page of data comprising the predefined data pattern for programming the third page.

10. The method of claim 1, wherein the predefined data pattern comprises error correction information for one or more of the data of the first page and the data of the second page.

11. The method of claim 1, wherein up to half of the abodes of the TLC mode are available to represent stored user data in the RLC mode.

12. An apparatus comprising:

a trigger module configured to determine whether an error rate for a set of non-volatile memory cells satisfies an error threshold;

a program module configured to write workload data to one or more lower and middle pages of the set of memory cells with each memory cell configured to represent at least three bits of data by way of one of a set of program states; and

an endurance module configured to write an endurance data pattern to an upper page of the set of memory cells instead of workload data to the upper page in response to the error rate satisfying the error threshold, thereby defining a subset of the program states of the set of memory cells for encoding workload data.

13. The apparatus of claim 12, further comprising a threshold module configured to adjust one or more thresholds for the program states of the set of memory cells in response to the error rate satisfying the error threshold to provide one or more separation distances between the subset of the program states selected for encoding workload data.

14. The apparatus of claim 12, further comprising a pattern module configured to determine the endurance pattern based on the workload data for the one or more lower and middle pages.

15. The apparatus of claim 12, further comprising a retirement module configured to retire the set of memory cells from storing workload data in response to the error rate satisfying a retirement error threshold.

16. The apparatus of claim 12, wherein the program module is further configured to write workload data to the upper page of the set of memory cells in response to the error rate failing to satisfy the error threshold.

17. The apparatus of claim 12, wherein the endurance data pattern is selected for use defining subsets of program states for different architectures of non-volatile memory cells, the different architectures comprising different arrangements of program states for a predefined data encoding for the program states of the non-volatile memory cells.

18. An apparatus comprising:

a trigger module configured to monitor an error rate for a region of non-volatile recording cells, each recording cell configured to encode at least three bits of data using a set of abodes;

a program module configured to cause user data to be programmed to the recording cells for two bits of the at least three bits of data; and

an endurance module configured to adjust one or more thresholds for the abodes of the recording cells, in response to the error rate satisfying an error threshold, to provide one or more separation distances between a subset of the abodes available for encoding the two bits of the at least three bits of data.

19. The apparatus of claim 18, wherein the third bit of the at least three bits of data is un-programmed in response to the error rate satisfying the error threshold.

20. The apparatus of claim 18, wherein the endurance module is configured to cause a data pattern to be programmed to the third bit of the at least three bits of data, the programming of the data pattern configured to determine which subset of the abodes is available for encoding the two bits of the at least three bits of data.

21. A method comprising:

receiving a write command to write data to an electronic memory device having multi-level cell (MLC) memory elements, wherein each MLC memory element is programmable to programming states in a MLC mode, wherein each programming state in the MLC mode is associated with at least a two bit encoding; and

programming at least one of the MLC memory elements to one of a plurality of programming states in a reduced-level cell (RLC) mode, wherein the programming states in the RLC mode exclude at least one of the programming states in the MLC mode, and the programming states in the RLC mode comprise first and second states used to represent a most significant bit (MSB) of the at least two bit encoding in the MLC mode.

22. The method of claim 21, further comprising dynamically switching between the MLC mode and a single level cell (SLC) mode in response to a trigger event by way of not addressing one or more pages comprising certain bits of the MLC memory elements.

23. The method of claim 21, wherein the first state comprises an erase state, the second state comprises a lower state of a pair of adjacent states of the designated programming states, and the pair of adjacent states of the designated programming states represent bit values with a common MSB value.

24-28. -28. (canceled)