METHOD AND APPARATUS FOR ROUTING DIE SIGNALS USING EXTERNAL INTERCONNECTS

• US 20140061642A1
• Filed: 03/14/2013
• Published: 03/06/2014
• Est. Priority Date: 08/31/2012
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Srinivas, Vaishnav, Brunolli, Michael, West, David Ian, Yang, Bernie Jord, Paynter, Charles David
• Granted Patent: US 9,871,012 B2
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/11462 Electroplating
• CPC Class Codes: H01L 2224/13028 the bump connector being disposed on at least two separate bonding areas, e.g. bond pads
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13109 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/13116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/14165 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2224/27462 Electroplating
• CPC Class Codes: H01L 2224/29028 the layer connector being disposed on at least two separate bonding areas, e.g. bond pads
• CPC Class Codes: H01L 2224/29078 being disposed next to each other, e.g. side-to-side arrangements
• CPC Class Codes: H01L 2224/29147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/3012 : Layout
• CPC Class Codes: H01L 2224/3213 : the layer connector connecting within a semiconductor or solid-state body, i.e. connecting two bonding areas on the same semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/831 : the layer connector being supplied to the parts to be connected in the bonding apparatus
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/30 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/381 : Pitch distance

Abstract

Various aspects of an approach for routing die signals in an interior portion of a die using external interconnects are described herein. The approach provides for contacts coupled to circuits in the interior portion of the die, where the contacts are exposed to an exterior portion of the die. The external interconnects are configured to couple these contacts so that signals from the circuits in the interior portion of the die may be routed externally to the die. In various aspects of the disclosed approach, the external interconnects are protected by a packaging for the die.

Claims

1. An apparatus comprising:

a die comprising an exterior portion, and an interior portion comprising a plurality of circuits, wherein the plurality of circuits in the interior portion comprises;

a first circuit formed in a first area of the die; and

a second circuit formed in a second area of the die;

first and second die exterior contacts on the exterior portion of the die, wherein the first die exterior contact is electrically connected to the first circuit and the second die exterior contact is electrically connected to the second circuit; and

,

an interconnect electrically connecting the first and second die exterior contacts and configured to couple the second circuit to the first circuit, wherein the interconnect is located on the exterior portion of the die.

2. The apparatus of claim 1, wherein the interconnect comprises at least one of copper or aluminum.

3. The apparatus of claim 1, wherein the interconnect comprises a plurality of conductive pillars.

4. The apparatus of claim 3, wherein the plurality of conductive pillars are formed as adjacent pillars being in physical contact with each other so as to form a bar shape.

5. The apparatus of claim 1, wherein the die and the interconnect each comprises a thickness, and the thickness of the interconnect is at least 5 times the thickness of the die.

6. The apparatus of claim 1, further comprising a package, wherein the die is supported by the package, and wherein the package comprises the interconnect.

7. The apparatus of claim 6, wherein the interconnect comprises a layer of conductive material formed in the package.

8. The apparatus of claim 6, wherein signals generated by the first circuit and fed to the second circuit remain between the package and the die.

9. The apparatus of claim 6, wherein signals generated by the first circuit and fed to the second circuit remain within the package.

10. The apparatus of claim 1, wherein at least one of the first and second die exterior contacts comprise a copper pillar.

11. The apparatus of claim 1, wherein the first and second die exterior contacts are further coupled to a routing layer under the exterior portion of the die, wherein the routing layer is configured to separately couple the first die exterior contact to the first circuit, and the second die exterior contact to the second circuit, respectively.

12. The apparatus of claim 1, wherein the first circuit comprises a signal source and the second circuit comprises a signal sink.

13. The apparatus of claim 12, wherein the signal source is a clock circuit.

14. The apparatus of claim 1, wherein the first circuit comprises a clock generator configured to provide a clock signal.

15. The apparatus of claim 1, wherein the plurality of circuits in the interior portion of the die further comprises a testing circuit configured to couple the first and second circuits during a testing mode.

16. The apparatus of claim 15, wherein the testing circuit comprises a multiplexer configured to allow selection between the testing circuit and the interconnect to couple the first and second circuits.

17. The apparatus of claim 15, wherein only the testing circuit couples the first and second circuits during the testing mode.

18. The apparatus of claim 15, wherein the testing circuit is inoperable to couple the first circuit to the second circuit other than during the testing mode.

19. An apparatus comprising:

a die comprising an exterior portion and an interior portion comprising a plurality of circuits, wherein the plurality of circuits in the interior portion comprising;

a first circuit formed in a first area of the die; and

a second circuit formed in a second area of the die;

first and second exterior contact means on the exterior portion of the die, wherein the first exterior contact means is electrically connected to the first circuit and the second exterior contact means is electrically connected to the second circuit; and

,

interconnect means for electrically connecting the second circuit to the first circuit, wherein the interconnect means is located on the exterior portion of the die.

20. The apparatus of claim 19, wherein the interconnect means comprises at least one of copper or aluminum.

21. The apparatus of claim 19, wherein the interconnect means comprises a plurality of conductive pillars.

22. The apparatus of claim 21, wherein the plurality of conductive pillars are formed as adjacent pillars being in physical contact with each other so as to form a bar shape.

23. The apparatus of claim 19, wherein the die and the interconnect means each comprises a thickness, and the thickness of the interconnect means is at least 5 times the thickness of the die.

24. The apparatus of claim 19, further comprising a package, wherein the die is supported by the package, and wherein the package comprises the interconnect means.

25. The apparatus of claim 24, wherein the interconnect means comprises a layer of conductive material formed in the package.

26. The apparatus of claim 24, wherein signals generated by the first circuit and fed to the second circuit remains between the package and the die.

27. The apparatus of claim 24, wherein signals generated by the first circuit and fed to the second circuit remain within the package.

28. The apparatus of claim 19, wherein at least one of the first and second exterior contact means comprise a copper pillar.

29. The apparatus of claim 19, wherein the first and second exterior contact means are further coupled to a routing layer under the exterior portion of the die, wherein the routing layer is configured to separately couple the first exterior contact means to the first circuit, and the second exterior contact means to the second circuit, respectively.

30. The apparatus of claim 19, wherein the first circuit comprises means for generating a signal and the second circuit comprises a signal sink.

31. The apparatus of claim 30, wherein the means for generating the signal is a clock circuit.

32. The apparatus of claim 19, wherein the plurality of circuits in the interior portion of the die further comprises testing means configured to couple the first and second circuits during a testing mode.

33. The apparatus of claim 32, wherein the testing means comprises a multiplexer configured to allow selection between a testing circuit and the interconnect means to couple the first and second circuits.

34. The apparatus of claim 32, wherein only the testing means couples the first and second circuits during the testing mode.

35. The apparatus of claim 32, wherein the testing means is inoperable to couple the first circuit to the second circuit other than during the testing mode.

36. A semiconductor device comprising:

a die comprising an exterior portion and an interior portion comprising a plurality of circuits, wherein the plurality of circuits in the interior portion comprising;

a first circuit formed in a first area of the die; and

a second circuit formed in a second area of the die;

first and second die exterior contacts on the exterior portion of the die,

wherein the first die exterior contact is coupled to the first circuit and the second die exterior contact is coupled to the second circuit; and

a package comprising an interconnect coupled to the first and second die exterior contacts and configured to couple the second circuit to the first circuit, wherein the package is located on the exterior portion of the die.

37. A method comprising:

exposing a plurality of contacts on an exterior portion of a die, wherein the plurality of contacts comprises a first contact coupled to a first circuit, and a second contact coupled to a second circuit, wherein the first and second circuits are in an interior portion of the die; and

coupling at least two contacts in the plurality of contacts via at least one interconnect external to the die to connect the first and the second circuits in the interior portion of the die.