NITRIDE SEMICONDUCTOR WAFER, NITRIDE SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR WAFER

• US 20140061693A1
• Filed: 09/25/2012
• Published: 03/06/2014
• Est. Priority Date: 09/05/2012
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Hisashi Yoshida
• Inventors: YOSHIDA, Hisashi, Hikosaka, Toshiki, Harada, Yoshiyuki, Sugiyama, Naoharu, Nunoue, Shinya
• Granted Patent: US 9,053,931 B2
• Time in Patent Office: Days
• US Class Current: 257/94
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD

Abstract

According to one embodiment, a nitride semiconductor wafer includes: a silicon substrate; a buffer section provided on the silicon substrate; and a functional layer provided on the buffer section and contains nitride semiconductor. The buffer section includes first to n-th buffer layers (n being an integer of 4 or more) containing nitride semiconductor. An i-th buffer layer (i being an integer of 1 or more and less than n) of the first to n-th buffer layers has a lattice length Wi in a first direction parallel to a major surface of the first buffer layer. An (i+1)-th buffer layer provided on the i-th buffer layer has a lattice length W(i+1) in the first direction. In the first to n-th buffer layers the i-th buffer layer and the (i+1)-th buffer layer satisfy relation of (W(i+1)−Wi)/Wi≦0.008.

Claims

1. A nitride semiconductor wafer comprising:

a silicon substrate;

a buffer section provided on the silicon substrate and including first to n-th buffer layers (n being an integer of 4 or more) containing nitride semiconductor, an i-th buffer layer (i being an integer of 1 or more and less than n) of the first to n-th buffer layers having a lattice length Wi in a first direction parallel to a major surface of the first buffer layer, an (i+1)-th buffer layer provided on the i-th buffer layer having a lattice length W(i+1) in the first direction, and in the first to n-th buffer layers the i-th buffer layer and the (i+1)-th buffer layer satisfying relation of (W(i+1)−

Wi)/Wi≦

0.008; and

a functional layer provided on the buffer section and containing nitride semiconductor.

2. The wafer according to claim 1, wherein in the first to n-th buffer layers the i-th buffer layer and the (i+1)-th buffer layer satisfy relation of 0.003≦

(W(i+1)−

Wi)/Wi.

3. The wafer according to claim 1, wherein the (i+1)-th buffer layer is in contact with the i-th buffer layer.

4. The wafer according to claim 1, wherein

the major surface is a c-plane, and

the first direction is an a-axis direction.

5. The wafer according to claim 1, wherein

the first buffer layer contains Al_x1Ga_1-x1N (0<

x1≦

1),

the n-th buffer layer contains Al_xnGa_1-xnN (0≦

xn<

1), and

the i-th buffer layer between the first buffer layer and the n-th buffer layer contains Al_xiGa_1-xiN (0<

xi<

1).

6. The wafer according to claim 5, wherein Al composition ratio of the (i+1)-th buffer layer is lower than Al composition ratio of the i-th buffer layer.

7. The wafer according to claim 1, wherein lattice mismatch in the first direction between the first buffer layer and the n-th buffer layer is 1.9% or more and 2.5% or less.

8. The wafer according to claim 1, wherein the n is 9 or less.

9. The wafer according to claim 1, wherein the (i+1)-th buffer layer has a relaxation of 0.65 or less.

10. The wafer according to claim 1, wherein the functional layer includes:

a first semiconductor layer of a first conductivity type provided on the buffer section;

a light emitting layer provided on the first semiconductor layer; and

a second semiconductor layer of a second conductivity type provided on the light emitting layer.

11. The wafer according to claim 10, wherein

the light emitting layer includes a plurality of barrier layers and a well layer provided between the plurality of barrier layers, and

bandgap energy of the barrier layer is larger than bandgap energy of the well layer.

12. The wafer according to claim 11, wherein

the barrier layer contains a nitride semiconductor containing a group III element and a group V element, and

the well layer contains a nitride semiconductor containing a group III element and a group V element.

13. The wafer according to claim 10, wherein

the functional layer further includes a multilayer section provided between the first semiconductor layer and the light emitting layer,

the multilayer section includes a plurality of high bandgap energy layers and a low bandgap energy layer provided between the plurality of high bandgap energy layers, and

bandgap energy of the low bandgap energy layer is lower than bandgap energy of the high bandgap energy layer.

14. The wafer according to claim 1, further comprising:

an intermediate layer provided between the buffer section and the functional layer,

wherein the intermediate layer includes a first layer containing a nitride semiconductor containing Al, and a second layer provided on the first layer and containing a nitride semiconductor having a lower Al composition ratio than the first layer.

15. The wafer according to claim 14, wherein

the intermediate layer further includes a third layer containing a nitride semiconductor containing Al and provided between the first layer and the second layer, and

Al composition ratio of the third layer is lower than the Al composition ratio of the first layer and higher than the Al composition ratio of the second layer.

16. The wafer according to claim 1, further comprising:

a foundation layer provided between the buffer section and the functional layer and containing nitride semiconductor,

wherein concentration of impurity contained in the nitride semiconductor of the foundation layer is lower than concentration of impurity contained in the nitride semiconductor of the functional layer.

17. The wafer according to claim 1, wherein

the functional layer includes a third semiconductor layer provided on the buffer section, and a fourth semiconductor layer provided on the third semiconductor layer and forming a heterojunction with the third semiconductor layer, and

bandgap of the fourth semiconductor layer is larger than bandgap of the third semiconductor layer.

18. The wafer according to claim 17, wherein lattice constant of the fourth semiconductor layer is smaller than lattice constant of the third semiconductor layer.

19. A nitride semiconductor device comprising:

a buffer section formed on a silicon substrate and including first to n-th buffer layers (n being an integer of 4 or more) containing nitride semiconductor, an i-th buffer layer (i being an integer of 1 or more and less than n) of the first to n-th buffer layers having a lattice length Wi in a first direction parallel to a major surface of the first buffer layer, an (i+1)-th buffer layer provided on the i-th buffer layer having a lattice length W(i+1) in the first direction, and in the first to n-th buffer layers the i-th buffer layer and the (i+1)-th buffer layer satisfying relation of (W(i+1)−

Wi)/Wi≦

0.008; and

a functional layer provided on the buffer section and containing nitride semiconductor.

20. A method for manufacturing a nitride semiconductor wafer, comprising:

forming a buffer section on a silicon substrate, the buffer section including first to n-th buffer layers (n being an integer of 4 or more) containing nitride semiconductor, an i-th buffer layer (i being an integer of 1 or more and less than n) of the first to n-th buffer layers having a lattice length Wi in a first direction parallel to a major surface of the first buffer layer, an (i+1)-th buffer layer provided on the i-th buffer layer having a lattice length W(i+1) in the first direction, and in the first to n-th buffer layers the i-th buffer layer and the (i+1)-th buffer layer satisfying relation of (W(i+1)−

Wi)/Wi≦

0.008; and

forming a functional layer containing nitride semiconductor on the buffer section.