HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF MANUFACTURING THE SAME

• US 20140061725A1
• Filed: 01/30/2013
• Published: 03/06/2014
• Est. Priority Date: 09/04/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: PARK, Ki-yeol, JEON, Woo-chul, PARK, Young-hwan, SHIN, Jai-kwang, HA, Jong-bong, HWANG, Sun-kyu
• Granted Patent: US 8,860,089 B2
• Time in Patent Office: Days
• US Class Current: 257/194
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/66431 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT with an active layer made of a group 13/15 material H01L29/66462
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/778 with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface H01L29/803 takes precedence
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Abstract

According to example embodiments, a higher electron mobility transistor (HEMT) may include a first channel layer, a second channel layer on the first channel layer, a channel supply on the second channel layer, a drain electrode spaced apart from the first channel layer, a source electrode contacting the first channel layer and contacting at least one of the second channel layer and the channel supply layer, and a gate electrode unit between the source electrode and the drain electrode. The gate electrode unit may have a normally-off structure. The first and second channel layer form a PN junction with each other. The drain electrode contacts at least one of the second channel layer and the channel supply layer.

Claims

1. A high electron mobility transistor comprising:

a first channel layer;

a second channel layer on the first channel layer,

the second channel layer forming a PN junction with the first channel layer;

a channel supply layer on the second channel layer;

a drain electrode spaced apart from the first channel layer,

the drain electrode contacting at least one of the second channel layer and the channel supply layer;

a source electrode contacting the first channel layer and contacting at least one of the second channel layer and the channel supply layer; and

a gate electrode unit between the source electrode and the drain electrode,

the gate electrode unit having a normally-off structure.

2. The high electron mobility transistor of claim 1, wherein

the first channel layer is a p-type semiconductor layer, and

the second channel layer is an n-type semiconductor layer.

3. The high electron mobility transistor of claim 2, wherein the first channel layer is a p-type doped GaN layer.

4. The high electron mobility transistor of claim 2, wherein the second channel layer is one of an undoped GaN layer and an n-type doped GaN layer.

5. The high electron mobility transistor of claim 1, wherein

at least one of the channel supply layer and the second channel layer defines a source electrode accommodation portion, and

the source electrode is in the source electrode accommodation portion.

6. The high electron mobility transistor of claim 5, wherein

the source electrode accommodation portion is a recessed towards the first channel layer.

7. The high electron mobility transistor of claim 6, wherein the source electrode accommodation portion extends to one of:

an interface between the first channel layer and the second channel layer, and

a deeper depth than the interface between the first channel layer and the second channel layer.

8. The high electron mobility transistor of claim 1, wherein source electrode includes:

a first area of the source electrode that is in ohmic contact with the first channel layer; and

a second area of the source electrode that is in ohmic contact with at least one of the second channel layer and the channel supply layer.

9. The high electron mobility transistor of claim 8, wherein

the first area of the source electrode is in p-type ohmic contact with the first channel layer, and

the second area of the source electrode is in n-type ohmic contact with at least one of the second channel layer and the channel supply layer.

10. The high electron mobility transistor of claim 1, wherein a bandgap of the channel supply layer is greater than a bandgap of the second channel layer.

11. The high electron mobility transistor of claim 1, wherein

the gate electrode unit includes,

a gate electrode between the source electrode and the drain electrode, and

a gate electrode accommodation portion defined by the channel supply layer and the second channel layer;

and

the gate electrode is in the gate electrode accommodation portion.

12. The high electron mobility transistor of claim 11, wherein

the gate electrode accommodation portion is a recessed towards the first channel layer.

13. The high electron mobility transistor of claim 12, further comprising:

an insulating layer between the gate electrode and the gate electrode accommodation portion.

14. The high electron mobility transistor of claim 1, wherein the gate electrode unit includes:

a gate electrode between the source electrode and the drain electrode; and

a channel depletion layer between the gate electrode and the channel supply layer.

15. The high electron mobility transistor of claim 14, wherein the channel depletion layer includes a p-type semiconductor layer.

16. A method of manufacturing a high electron mobility transistor, the method comprising:

forming a first channel layer;

forming a second channel layer on the first channel layer,

the first channel layer and the second channel layer forming a PN junction with each other;

forming a channel supply layer on the second channel layer;

forming a source electrode accommodation portion defined by the second channel layer and the channel supply layer,

the source electrode accommodation portion exposing a part of the first channel layer;

forming a source electrode in the source electrode accommodation portion, the source electrode contacting the first channel layer;

forming a drain electrode that is spaced apart from the first channel layer and contacts at least one of the second channel layer and the channel supply layer; and

forming a gate electrode unit between the source electrode and the drain electrode,

the gate electrode unit having a normally-off structure.

17. The method of claim 16, wherein the forming the source electrode accommodation portion includes forming the source electrode accommodation portion to one of:

an interface between the first channel layer and the second channel layer, and

a deeper depth than the interface between the first channel layer and the second channel layer.

18. The method of claim 16, wherein the forming the source electrode includes:

forming a first area of the source electrode that is in ohmic contact with the first channel layer; and

forming a second area of the source electrode that is in ohmic contact with at least one of the second channel layer and the channel supply layer.

19. The method of claim 16, wherein the forming the gate electrode unit includes:

forming a gate electrode accommodation portion as a recess defined the channel supply layer and the second channel layer that is between the source electrode and the drain electrode; and

forming a gate electrode in the gate electrode accommodation portion.

20. The method of claim 19, further comprising:

forming an insulating layer on the gate electrode accommodation portion before the forming the gate electrode.

21. The method of claim 16, wherein the forming the gate electrode unit includes:

forming a channel depletion layer between the source electrode and the drain electrode; and

forming the gate electrode on the channel depletion layer.