MEMORY ARRAY HAVING CONNECTIONS GOING THROUGH CONTROL GATES

• US 20140061747A1
• Filed: 08/30/2012
• Published: 03/06/2014
• Est. Priority Date: 08/30/2012
• Status: Active Grant

• Current Assignee: Lodestar Licensing Group LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Tanzawa, Toru, Murakoshi, Tamotsu, Thimmegowda, Deepak
• Granted Patent: US 9,595,533 B2
• Time in Patent Office: Days
• US Class Current: 257/314
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 43/00 EEPROM devices comprising charge-trapping gate insulators
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions
• CPC Class Codes: H10B 61/20 comprising components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type

Abstract

Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus and along a portion of the body, and control gates located in other levels of the apparatus and along other respective portions of the body. At least one of such apparatuses includes a conductive connection coupling the select gate or one of the control gates to a component (e.g., transistor) in the substrate. The connection can include a portion going through a portion of at least one of the control gates.

Claims

1. An apparatus comprising:

a substrate;

a memory cell string including a body and memory cells located in different levels of the apparatus;

a first conductive material over the substrate, the first conductive material including a portion opposing a first portion of the body;

a second conductive material over the substrate, the second conductive material including a portion opposing a second portion of the body;

a first connection coupled to a first contact area of the first conductive material and to a first conductive contact located between the first conductive material and the substrate; and

a second connection coupled to a second contact area of the second conductive material and to a second conductive contact located between the second conductive material and the substrate, wherein the second connection includes a segment between the first and second contact areas and extending from one level to another level of the apparatus.

2. The apparatus of claim 1, wherein the first conductive material is part of a select gate associated with the memory cell string.

3. The apparatus of claim 1, wherein the first conductive material is part of a control gate associated with the memory cell string.

4. The apparatus of claim 1, wherein the first conductive material is part of a control gate associated with the memory cell string, and the second conductive material is part of a control gate associated with the memory cell string.

5. The apparatus of claim 1, wherein the first conductive material is part of a first control gate associated with the memory cell string, and the second conductive material is part of a second control gate associated with the memory cell string.

6. The apparatus of claim 1, wherein the second connection includes a first segment perpendicular to the substrate, a second segment perpendicular to the substrate, and a third segment coupling the first segment to the second segment, the third segment being parallel to the substrate.

7. The apparatus of claim 6, wherein the second segment of the second connection includes the segment between the first and second contact areas.

8. The apparatus of claim 1, wherein the apparatus comprises a memory device, the memory device comprising the memory cell string.

9. An apparatus comprising:

a substrate;

a memory cell string including a body;

a select gate located in a first level of the apparatus and along a first portion of the body;

a control gate located in a second level of the apparatus and along a second portion of the body; and

a connection coupled to the select gate and to a transistor having at least a portion formed in the substrate, the connection including a portion going through a portion of the control gate.

10. The apparatus of claim 9, further comprising an opening through the control gate, wherein the portion of the connection going through the portion of the control gate is inside the opening.

11. The apparatus of claim 9, further comprising an additional control gate located in a third level of the apparatus and along a third portion of the body, wherein the connection includes an additional portion going through a portion of the additional control gate.

12. The apparatus of claim 11, further comprising an opening through the control gate and the additional control gate, wherein the portion of the connection going through the portion of the control gate is inside the opening, and the additional portion of the connection going through the portion of the additional portion of the control gate is also inside the opening.

13. The apparatus of claim 12, wherein the select gate includes an edge, the control gate includes an edge, and the opening is between the edge of the select gate and the edge of the control gate.

14. The apparatus of claim 13, wherein the distance between the body and the edge of the control gate is greater than a distance between the body and the edge of the select gate.

15. The apparatus of claim 10, further comprising:

an additional memory cell string including an additional body extending outwardly from the substrate;

an additional select gate located in the first level of the apparatus and along a portion of the additional body; and

an additional connection coupled to the additional select gate and to an additional transistor having at least a portion formed in the substrate, the additional connection including a portion going through an additional opening in the control gate.

16. An apparatus comprising:

a substrate;

a memory cell string including a body;

a first control gate located in a first level of the apparatus and along a first portion of the body;

a second control gate located in a second level of the apparatus and along a second portion of the body; and

a connection coupled to the second control gate and to a transistor having at least a portion formed in the substrate, the connection including a portion going through a portion of the first control gate.

17. The apparatus of claim 16, further comprising an opening through the first control gate, wherein the portion of the connection going through the portion of the first control gate is inside the opening.

18. The apparatus of claim 17, wherein the first control gate includes an edge, the second control gate includes an edge, and the opening is between the edge of the first control gate and the edge of the second control gate.

19. The apparatus of claim 18, wherein the distance between the body and the edge of the first control gate is greater than a distance between the body and the edge of the second control gate.

20. The apparatus of claim 17, further comprising:

a third control gate located in a third level of the apparatus and along a third portion of the body; and

an additional connection coupled to the third control gate and to an additional transistor having at least a portion formed in the substrate, the additional connection including a portion going through an additional opening in the first control gate.

21. The apparatus of claim 16, further comprising a third control gate located in a third level of the apparatus and along a third portion of the body, wherein the connection includes another portion going through a portion of the third control gate.

22. An apparatus comprising:

a first memory array including a first memory cell string over a substrate, and a first select gate and control gates located along a body of the first memory string and over the substrate;

a second memory array including a second memory cell string over the substrate, and a second select gate and control gates located along a body of the second memory string and over the substrate;

a first connection coupled to the first select gate and including a portion going through a portion of a first control gate among the control gates of the first memory array;

a second connection coupled to the second select gate and including a portion going through a portion of a second control gate among the control gates of the second memory array; and

a third connection coupling the first connection to the second connection.

23. The apparatus of claim 22, wherein the third connection includes a segment parallel to substrate.

24. The apparatus of claim 23, wherein the first connection includes a first segment perpendicular to the substrate, a second segment perpendicular to the substrate, and a third segment coupling the first segment to the second segment, the third segment being parallel to the substrate.

25. The apparatus of claim 24, wherein the second connection includes a first segment perpendicular to the substrate, a second segment perpendicular to the substrate, and a third segment coupling the first segment to the second segment, the third segment being parallel to the substrate.

26. The apparatus of claim 22, further including a transistor coupled to the third connection.

27. The apparatus of claim 26, wherein the transistor include source and drain regions formed in an area of the substrate, the area of the substrate being under and between the first and second arrays.

28. The apparatus of claim 26, wherein the transistor includes source and drain regions formed in an area of the substrate, the area of the substrate being under the first array.

29. An apparatus comprising:

a first conductive material located in a first level of the apparatus;

a second conductive material located in a second level of the apparatus;

a third conductive material located in a third level of the apparatus; and

a connection coupled to a contact area of the first conductive material and to a contact area of the third conductive material, the connection including a portion going through a portion of the second conductive material, wherein the portion of the second conductive material is between an edge of the second conductive material and an edge of the third material.

30. The apparatus of claim 29, wherein the second conductive material includes an opening, and the portion of the connection is inside the opening.

31. The apparatus of claim 29, wherein the second and third conductive materials have a same width.

32. The apparatus of claim 29, wherein the second and third conductive materials have different widths.

33. The apparatus of claim 29, further comprising a fourth conductive material located in the first level, and an additional connection coupled to a contact area of the fourth conductive material and to a contact area of the second conductive material, wherein the edge of the second conductive is between the contact area of the second conductive material and the contact area of the fourth conductive material.

34. A method comprising:

forming a first control gate, a second control gate, and a select gate in different levels of a device over a substrate of the device;

forming an opening in an area of the device between an edge of the first control gate and an edge of one of the select gate and the second control gate; and

forming a connection coupling one of the select gate and the second control gate to a conductive contact located between the substrate and the first control gate, wherein the connection is formed such that a portion of the connection is inside the opening.

35. The method of claim 34, wherein the opening is formed such that a bottom of the opening is coupled to the conductive contact.

36. The method of claim 34, wherein forming the opening includes:

removing material from part of the first control gate to form an opening through the first control gate;

filling the opening with a dielectric material; and

forming the opening in the dielectric material, such that the opening is separated from remaining portions of the control gates by a portion of the dielectric material.

37. The method of claim 36, wherein forming the connection includes filling the opening with a conductive material.

38. The method of claim 34, wherein forming the connection includes:

forming a first segment of the connection such that the first segment is coupled to one of the select gate and the second control gate and extends in a direction perpendicular to the substrate;

forming a second segment of the connection in the opening; and

forming a third segment to couple the first segment to the second segment.

39. A method comprising:

forming a first group of control gates and a second group of control gates on different levels of a device over a substrate of the device;

forming an opening through the first group of control gates; and

forming a connection coupling a control gate in the second group of control gates to a conductive contact located between the first and second groups of control gates and the substrate, wherein the connection is formed such that a portion of the connection is inside the opening.

40. The method of claim 39, wherein forming the opening includes:

removing material from part of each control gate in the first group of the control gates to form a first opening through the first group of control gates;

filling the first opening with a dielectric material; and

forming a second opening in the dielectric material, such that the second opening is separated from remaining portions of the first group of control gates by a portion of the dielectric material.

41. The method of claim 40, wherein forming the connection includes filling the second opening with a conductive material.

42. The method of claim 39, further comprising:

forming an additional opening through the first group of control gates;

forming an additional connection coupling an additional control gate in the second group of control gates to an additional conductive contact located between the first and second groups of control gates and the substrate, wherein the additional connection is formed such that a portion of the additional connection is inside the additional opening.