SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

• US 20140061788A1
• Filed: 10/08/2013
• Published: 03/06/2014
• Est. Priority Date: 08/31/2012
• Status: Active Grant

• Current Assignee: Nuvoton Technology Corporation (Winbond Electronics Corporation)
• Original Assignee: Nuvoton Technology Corporation (Winbond Electronics Corporation)
• Inventors: Chen, Po-An, Sheu, Gene, Yang, Shao-Ming, Siddiqui, MD Imran
• Granted Patent: US 8,912,599 B2
• Time in Patent Office: Days
• US Class Current: 257/339
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

A semiconductor device is provided. The semiconductor device includes a drain region, a source region, a channel region and a hybrid doped region. The drain region of a first conductivity type is located in a substrate. The source region of the first conductivity type is located in the substrate and surrounding the drain region. The channel region is located in the substrate between the source region and the drain region. The hybrid doped region includes a top doped region and a compensation doped region. The top doped region is of a second conductivity type, having a doping concentration decreased from a region near the channel region to a region near the drain region, and located in the substrate between the channel region and the drain region. The compensation doped region of the first conductivity type is located in the top doped region to compensate the top doped region.

Claims

1. A semiconductor device, comprising:

a drain region of a first conductivity type located in a substrate;

a source region of the first conductivity type, located in the substrate;

a channel region located in a portion of the substrate between the source region and the drain region;

a gate covering the channel region and the portion of the substrate; and

a hybrid doped region located in the substrate between the channel region and the drain region, and the hybrid doped region comprising;

a top doped region of a second conductivity type, located in the substrate between the channel region and the drain region, and the top doped region having a doping concentration gradually decreased from a region near the channel region to a region near the drain region; and

a compensation doped region of the first conductivity type, located in the top doped region to compensate the top doped region.

2. The semiconductor device of claim 1, wherein

the top doped region is a first linear doped region having a concentration gradually decreased from the region near the channel region to the region near the drain region;

and

the compensation doped region is a block-shape region having a uniform doping concentration.

3. The semiconductor device of claim 1, wherein

the top doped region is a first linear doped region having a concentration gradually decreased from the region near the channel region to the region near the drain region;

and

the compensation doped region is a second linear doped region having a concentration gradually decreased from the region near the channel region to the region near the drain region.

4. The semiconductor device of claim 1, wherein

the top doped region has the doping concentration gradually decreased from the region near the channel region to the region near the drain region;

and

the compensation doped region is a linear doped region having a concentration gradually increased from the region near the channel region to the region near the drain region.

5. The semiconductor device of claim 1, further comprising:

a first doped region of the first conductivity type, located in the substrate around the drain region, wherein the hybrid doped region and the drain region are located in the first doped region;

a second doped region of the first conductivity type, located in the substrate around the source region;

a third doped region of the second conductivity type, located in the second doped region;

a fourth doped region of the first conductivity type, located in the first doped region and adjacent to the hybrid doped region; and

two heavily doped regions of the first conductivity type, respectively located in the fourth doped region and the third doped region, wherein the drain region and the source region are respectively located in the two heavily doped regions.

6. The semiconductor device of claim 1, further comprising a fifth doped region of the second conductivity type, wherein the fifth doped region is adjacent to the drain region.

7. The metal oxide semiconductor transistor according to claim 1, wherein the first conductivity type is an N-type while the second conductivity type is a P-type;

and the first conductivity type is a P-type while the second conductivity type is an N-type.

8. The semiconductor device of claim 1, wherein the drain region is surrounded and completely enclosed by the source region.

9. A method of fabricating a semiconductor device, comprising:

forming a top doped region of a second conductivity type;

forming a compensation doped region of a first conductivity type, and the compensation doped region being located in the top doped region,

forming a drain region on a first side of the top doped region, and the drain region being of the first conductivity type; and

forming a source region on a second side of the top doped region, the source region being of the first conductivity type, wherein a channel region in a portion of a substrate between the source region and the drain region,

wherein a doping concentration of the top doped region is gradually decreased from a region near the channel region to a region near the drain region.

10. The method of fabricating the semiconductor device of claim 9, wherein the step of forming the top doped region and the step of forming the compensation doped region, comprising:

forming a first patterned mask layer, and the first patterned mask layer having at least one first opening;

performing a first ion implantation process to form the top doped region by using the first patterned mask layer as a mask;

removing the first patterned mask layer;

forming a second patterned mask layer, the second patterned mask layer having at least one second opening exposing the top doped region;

performing a second ion implantation process to form the compensation doped region in the top doped region by using the second patterned mask layer as a mask; and

removing the second patterned mask layer.

11. The method of fabricating the semiconductor device of claim 10, wherein the first patterned mask layer comprises a plurality of first openings in which a dimension of the first openings being gradually decreased from the region near the channel region to the region near the drain region, and a pitch between the first openings being gradually decreased from the region near the channel region to the region near the drain region.

12. The method of fabricating the semiconductor device of claim 11, further comprising performing an annealing process to smooth a profile of the top doped region.

13. The method of fabricating the semiconductor device of claim 10, wherein the first patterned mask layer has the first opening, and the top doped region formed by the first ion implantation process has a uniform doping concentration.

14. The method of fabricating the semiconductor device of claim 13, wherein the second patterned mask layer comprises a plurality of second openings in which a dimension of the second openings being gradually increased from the region near the channel region to the region near the drain region, and a pitch between the second openings being gradually increased from the region near the channel region to the region near the drain region.

15. The method of fabricating the semiconductor device of claim 14, further comprising performing an annealing process to smooth a profile of the compensation doped region.

16. The method of fabricating the semiconductor device of claim 9, further comprising:

forming a first doped region of the first conductivity type around the drain region, wherein the top doped region, the compensation doped region and the drain region are located in the first doped region;

forming a second doped region of the first conductivity type around the source region;

forming a third doped region of the second conductivity type in the second doped region;

forming a fourth doped region of the first conductivity type in the first doped region, and the fourth doped region being adjacent to the top doped region and the compensation doped region; and

forming a heavily doped region of the first conductivity type respectively in the fourth doped region and the third doped region, wherein the drain region and the source region are respectively located in the corresponding heavily doped region.

17. The method of fabricating the semiconductor device of claim 9, wherein the first conductivity type is an N-type while the second conductivity type is a P-type;

and the first conductivity type is a P-type while the second conductivity type is an N-type.

18. A metal oxide semiconductor transistor, comprising:

a drain region of a first conductivity type located in a substrate;

a source region of the first conductivity type, located in the substrate;

a gate located above the substrate between the source region and the drain region;

a gate dielectric layer located between the gate and the substrate; and

a compensation doped region of the first conductivity type, located in the substrate between the source region and the drain region; and

a top doped region of a second conductivity type, located below the compensation doped region, and having a doping concentration gradually decreased from a region near the source region to a region near the drain region.

19. A method of fabricating a semiconductor device, comprising:

forming an N-type doped layer in a substrate;

forming a top doped region of a P-type in the N-type doped layer between a region predetermined for forming a drain region and a region predetermined for forming a channel region;

implanting an N-type dopant in the top doped region to form a compensation doped region in the top doped region;

forming the drain region of an N-type in the N-type doped layer; and

forming a source region of the N-type conductivity type on a side of the channel region.

20. The method of fabricating the semiconductor device of claim 19, wherein the drain region is surrounded and completely enclosed by the source region.