SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF

• US 20140061917A1
• Filed: 06/28/2013
• Published: 03/06/2014
• Est. Priority Date: 08/28/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Dong-Kwon Kim, Ki-Il Kim
• Inventors: KIM, DONG-KWON, KIM, KI-IL
• Granted Patent: US 9,087,844 B2
• Time in Patent Office: Days
• US Class Current: 257/751
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76813 involving a partial via etch
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device includes a lower conductor having a lower conductor sidewall, a barrier film having a barrier film sidewall formed directly on the lower conductor sidewall, and a via formed on a top surface of the lower conductor. A top portion of the barrier film sidewall is recessed, such that a top surface of the barrier film sidewall is at a level lower than the top surface of the lower conductor.

Claims

1. A semiconductor device comprising:

a lower conductor having a lower conductor sidewall;

a barrier film having a barrier film sidewall formed directly on the lower conductor sidewall; and

a via formed on a top surface of the lower conductor,

wherein a top portion of the barrier film sidewall is recessed, such that a top surface of the barrier film sidewall is at a level lower than the top surface of the lower conductor.

2. The semiconductor device of claim 1, further comprising:

a first insulation film surrounding a combination of the lower conductor and the barrier film, wherein a portion of the first insulation film proximate the recessed top portion of the barrier film sidewall is recessed.

3. The semiconductor device of claim 2, wherein the recessed top portion of the barrier film and the recessed portion of the first insulation film collectively form a recessed region having a width that is upwardly increasing from the top surface of the barrier film.

4. The semiconductor device of claim 3, wherein the via extends to completely fill the recessed region.

5. The semiconductor device of claim 1, wherein a width of the top surface of the lower conductor is less than or equal to a width of a bottom surface of the via.

6. The semiconductor device of claim 1, further comprising:

a first upper conductor formed directly on the via and having opposing sidewalls that vertically align with respective opposing sidewalls of the via.

7. The semiconductor device of claim 6, further comprising:

a second upper conductor arranged in parallel with the first upper conductor and separated from the first upper conductor by a pitch that ranges from between about 10 nm to about 100 nm.

8. The semiconductor device of claim 6, wherein the via is a dual damascene via.

9. The semiconductor device of claim 1, wherein the barrier film comprises at least one of Ti and TiN.

10. The semiconductor device of claim 1, wherein the top surface of the lower conductor is relatively convex in shape.

11. A semiconductor device comprising:

a first lower conductor having a first lower conductor sidewall;

a second lower conductor having a second lower conductor sidewall, wherein the first lower conductor and the second lower conductor are disposed at a same metal layer of the semiconductor device;

a first barrier film having a first barrier film sidewall formed directly on the first lower conductor sidewall;

a second barrier film having a second barrier film sidewall formed directly on the second lower conductor sidewall; and

a via formed on a top surface of the first lower conductor, wherein a top portion of the first barrier film sidewall is recessed, such that a top surface of the first barrier film sidewall is at a level lower than the top surface of the first lower conductor.

12. The semiconductor device of claim 11, wherein a top surface of the second barrier film sidewall is at a same level as the top surface of the first lower conductor.

13. The semiconductor device of claim 11, further comprising:

a first insulation film surrounding a first combination of the first lower conductor and the first barrier film, and surrounding a second combination of the second lower conductor and the second barrier film,

wherein a portion of the first insulation film proximate the recessed top portion of the first barrier film sidewall is recessed.

14. The semiconductor device of claim 13, wherein the recessed top portion of the first barrier film and the recessed portion of the first insulation film collectively form a recessed region having a width that is upwardly increasing from the top surface of the first barrier film.

15. The semiconductor device of claim 14, wherein the via extends to completely fill the recessed region.

16. The semiconductor device of claim 11, wherein a width of the top surface of the first lower conductor is less than or equal to a width of a bottom surface of the via.

17. The semiconductor device of claim 11, further comprising:

a first upper conductor formed directly on the via and having opposing sidewalls that vertically align with respective opposing sidewalls of the via.

18. The semiconductor device of claim 17, further comprising:

a second upper conductor arranged in parallel with the first upper conductor and separated from the first upper conductor by a pitch that ranges from between about 10 nm to about 100 nm.

19. The semiconductor device of claim 11, wherein the top surface of the first lower conductor is relatively convex in shape, and a top surface of the second lower conductor is planar is shape.

20-27. -27. (canceled)