PHASE LOCKED LOOP

• US 20140062550A1
• Filed: 09/03/2013
• Published: 03/06/2014
• Est. Priority Date: 09/05/2012
• Status: Abandoned Application

• Current Assignee: Realtek Semiconductor Corp.
• Original Assignee: Realtek Semiconductor Corp.
• Inventors: Lee, Chao-Cheng, Zhao, Hai-Bing
• Application Number:
  US14/016,319
• Publication Number:
  US 20140062550A1
• Time in Patent Office: Days
• US Class Current: 327/157
• CPC Class Codes: H03L 7/0893 the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence

Abstract

A phase locked loop comprises a loop filter and a charge pump circuit. The loop filter comprises a parallel capacitor, a serial resistor and a serial capacitor. A first terminal of the serial resistor is electrically connected to a first terminal of the parallel capacitor. A first terminal of the serial capacitor is electrically connected to the second terminal of the serial resistor, and a second terminal of the serial capacitor is electrically connected to a second terminal of the parallel capacitor. The charge pump circuit comprises a first charge pump and a second charge pump. The first charge pump is electrically connected to the first terminal of the serial resistor, and the second charge pump is electrically connected to the second terminal of the serial resistor. The phase lock loop can reduce output jitter and therefore increases the performance of the phase lock loop.

Claims

1. A phase lock loop (PLL), comprising:

a loop filter and a charge pump circuit;

wherein

the loop filter comprises;

a parallel capacitor having a first terminal and a second terminal;

a serial resistor having a first terminal and a second terminal, wherein the first terminal of the serial resistor is electrically connected to the first terminal of the parallel capacitor; and

a serial capacitor having a first terminal and a second terminal, wherein the first terminal of the serial capacitor is electrically connected to the second terminal of the serial resistor, and the second terminal of the serial capacitor is electrically connected to the second terminal of the parallel capacitor; and

the charge pump circuit comprises;

a first charge pump electrically connected to the first terminal of the serial resistor; and

a second charge pump electrically connected to the second terminal of the serial resistor.

2. The phase lock loop according to claim 1, wherein the first charge pump comprises:

a first current source;

a first switch controlled by a first switch signal to electrically connect the first current source to the first terminal of the serial resistor;

a second current source; and

a second switch controlled by a second switch signal to electrically connect the second current source to the first terminal of the serial resistor.

3. The phase lock loop according to claim 2, wherein the current provided by the first current source is the same as the current provided by the second current source.

4. The phase lock loop according to claim 2, wherein the second charge pump comprises:

a third current source;

a third switch controlled by the second switch signal to electrically connect the third current source to the second terminal of the serial resistor;

a fourth current source; and

a fourth switch controlled by the first switch signal to electrically connect to the fourth current source the second terminal of the serial resistor.

5. The phase lock loop according to claim 4, wherein the current provided by the third current source is the same as the current provided by the fourth current source.

6. The phase lock loop according to claim 4, wherein the current provided by the first current source is different from the current provided by the third current source.

7. The phase lock loop according to claim 1, wherein the current charged into the first terminal of the serial resistor is different from the current discharged from the second terminal of the serial resistor.

8. The phase lock loop according to claim 1, wherein the loop filter further comprises:

a resistor having a first terminal and a second terminal, wherein the first terminal of the resistor is electrically connected to the first terminal of the serial resistor;

a capacitor having a first terminal and a second terminal, wherein the first terminal of the capacitor is electrically connected to the second terminal of the resistor, and the second terminal of the capacitor is electrically connected to the second terminal of the serial capacitor.

9. The phase lock loop according to claim 2, further comprising:

a voltage controlled oscillator used for generating an oscillation signal according to an output of the loop filter; and

a phase frequency detector used for providing the first switch signal and the second switch signal according to the oscillation signal and a clock signal.