SYSTEMS AND METHODS FOR MEASURING SHEET RESISTANCE

• US 20140062845A1
• Filed: 08/31/2012
• Published: 03/06/2014
• Est. Priority Date: 08/31/2012
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Saeedi, Saman, Youn, Sang Y., Jamal, Shafiq M., Brahma, Kingsuk, Syed, Taif A.
• Granted Patent: US 8,970,464 B2
• Time in Patent Office: Days
• US Class Current: 345/92
• CPC Class Codes: G01N 27/045 Circuits measuring resistance per se G01R27/00, e.g. G01R27/22
• CPC Class Codes: G06F 17/00 Digital computing or data processing equipment or methods, specially adapted for specific functions information retrieval, database structures or file system structures therefor G06F16/00
• CPC Class Codes: G09G 3/006 Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309
• CPC Class Codes: G09G 3/36 using liquid crystals
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers
• CPC Class Codes: H01L 21/28 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268 etching for patterning the electrodes H01L21/311, H01L21/3213; multistep manufacturing processes for data storage electrodes H01L29/4011

Abstract

The present disclosure is directed to systems and methods for determining sheet resistance values in a liquid crystal display (LCD) panel. In certain embodiments, a system for determining sheet resistance values in an LCD panel may include a display driver integrated circuit (IC). The display driver IC may include a first switch coupled to a first input/output (I/O) pad and a second I/O pad such that the first I/O pad is configured to couple to a voltage source and the second I/O pad is configured to couple to a current source. The display driver IC may also include a second switch coupled to a third I/O pad and the second I/O pa such that the second switch has substantially the same geometry as the first switch and the third I/O pad is configured to couple to a thin-film transistor (TFT) layer of the display panel.

Claims

1. A display driver integrated circuit (IC) for determining a sheet resistance of a display panel, comprising:

a first switch coupled to a first input/output (I/O) pad and a second I/O pad, wherein the first I/O pad is configured to couple to a voltage source and the second I/O pad is configured to couple to a current source; and

a second switch coupled to a third I/O pad and the second I/O pad, wherein the second switch has substantially the same geometry as the first switch, and wherein the third I/O pad is configured to couple to a thin-film transistor (TFT) layer of the display panel.

2. The display driver IC of claim 1, wherein the first switch and the second switch are metal-oxide-semiconductor field-effect transistor (MOSFET) switches.

3. The display driver IC of claim 1, wherein the second I/O pad is coupled to the current source via a flex-on-glass (FOG) circuit.

4. The display driver IC of claim 1, wherein the current source comprises a direct current (DC) source.

5. The display driver IC of claim 1, comprising a plurality of I/O pads configured to couple to a plurality of conductive layers coupled to the display driver IC.

6. The display driver IC of claim 5, wherein each of the plurality of conductive layers is different.

7. A system, comprising:

a display driver integrated circuit (IC), comprising;

a first switch coupled to a first input/output (I/O) pad and a second I/O pad, wherein the first I/O pad is coupled to a voltage source, and wherein the second I/O pad is coupled to a current source; and

a second switch coupled to a third I/O pad and the second I/O pad, wherein the third I/O pad is coupled to a thin-film transistor (TFT) layer of a liquid crystal display (LCD); and

a test circuit, comprising;

the current source; and

a controller configured to determine a resistance of the TFT layer by controlling the first switch, the second switch, and the current source.

8. The system of claim 7, wherein the controller is configured to determine the resistance of the TFT layer by:

measuring a first voltage at the second I/O pad when the first switch is closed;

measuring a second voltage at the second I/O pad when the first switch is closed and a first current is provided to the first switch via the current source;

determining a resistance of the first switch based at least in part on the first voltage, the second voltage, and the first current;

providing a second current from the current source to the second I/O pad when the first switch is open and the second switch is closed, wherein the second current is configured to bias the second switch such that a resistance of the second switch is substantially the same as the resistance of the first switch; and

determining the resistance of the TFT layer based at least in part on the second current and the resistance of the first switch.

9. The system of claim 8, wherein the first voltage and the second voltage are floating voltages.

10. The system of claim 8, wherein the resistance of the first switch is determined according to:

R_path=(V′

_i−

V_i)/I_test)

where R_path is the resistance of the first switch, V_i is the first voltage, V′

_i is the second voltage, and I_test is the first current.

11. The system of claim 8, wherein providing the second current from the current source to the second I/O pad comprises sweeping the current source until a third voltage at the second I/O pad is substantially equal to the second voltage.

12. The system of claim 11, wherein the resistance of the TFT layer is determined according to:

R_x=(V_x−

I<sub>test—

x</sub>*R_path)/I<sub>test—

x</sub>

where R_x is the resistance of the TFT layer, V_x is the third voltage, and I<sub>test—

x</sub> is the second current.

13. An electronic device, comprising:

a display comprising a chip-on-glass (COG) circuit and a flex-on-glass circuit (FOG), wherein the display is configured to display image data, and wherein the COG circuit comprises;

a first switch coupled to a first COG pad and a second COG pad disposed on the COG circuit, wherein the first COG pad is coupled to a voltage source the second COG pad is coupled to a FOG pad disposed on the FOG circuit; and

a second switch coupled to a third COG pad and the second COG pad, wherein the third COG pad is coupled to a thin-film transistor (TFT) layer of the display; and

a test circuit comprising a current source, wherein the test circuit is configured to couple the current source to the FOG pad.

14. The electronic device of claim 13, wherein the test circuit is configured to couple to the COG circuit and control operations of the first switch and the second switch.

15. The electronic device of claim 13, comprising a processor configured to couple to the test circuit and to the COG circuit, and wherein the processor is configured to determine a resistance of the TFT layer by:

measuring a first voltage at the FOG pad when the first switch is closed;

measuring a second voltage at the FOG pad when the first switch is closed and a first current is provided to the first switch via the current source;

determining a resistance of the first switch based at least in part on the first voltage, the second voltage, and the first current;

providing a second current from the current source to the FOG pad when the first switch is open and the second switch is closed, wherein the second current corresponds to when a voltage at the FOG pad is substantially equal to the second voltage; and

determining the resistance of the TFT layer based at least in part on the second current, the second voltage, and the resistance of the first switch.

16. The electronic device of claim 15, wherein the processor is configured to determine the resistance of the TFT layer at one or more times.

18. A liquid crystal display (LCD), comprising:

a test circuit comprising a current source;

a display driver integrated circuit (IC), comprising;

a first switch coupled to a first input/output (I/O) pad and a second I/O pad, wherein the first I/O pad is coupled to a voltage source, and wherein the second I/O pad is coupled to the current source; and

a second switch coupled to a third I/O pad and the second I/O pad, wherein the third I/O pad is coupled to a thin-film transistor (TFT) layer of the LCD; and

a controller configured to determine a resistance of the TFT layer by;

determining a resistance of the first switch based at least in part on a first current provided by the current source, a plurality of voltage values that correspond to when the first switch is closed and the current source is off and when the first switch is closed and the current source is on, and a first current provided by the current source when the first switch is closed and the current source is on; and

determining the resistance of the TFT layer based at least in part on the resistance of the first switch, a first voltage at the second I/O pad when the second switch is closed, and a second current provided by the current source.

19. The LCD of claim 18, wherein the second current is configured such that the first voltage is substantially the same as a second voltage at the second I/O pad that corresponds to when the first switch is closed and the current source is providing the first current.

20. A method for determining a quality of a display, comprising:

determining a resistance of a thin-film transistor (TFT) layer of the display by;

measuring a first voltage at a first I/O pad when a first switch coupled between the first I/O pad and a voltage source is closed;

measuring a second voltage at the first I/O pad when the first switch is closed and a first current is provided to the first switch via a current source;

determining a resistance of the first switch based at least in part on the first voltage, the second voltage, and the first current;

providing a second current from the current source to the first I/O pad when the first switch is open and a second switch is closed, wherein the second switch is coupled between the first I/O pad and the TFT layer, wherein the second current is configured to bias the second switch such that a resistance of the second switch is substantially the same as the resistance of the first switch; and

determining the resistance of the TFT layer based at least in part on the second current and the resistance of the first switch;

determining whether the resistance of the TFT layer is within limits; and

determining that the display has failed a quality assurance test when the resistance of the TFT layer is not within the limits.