SYSTEMS AND METHODS FOR MONITORING LCD DISPLAY PANEL RESISTANCE

• US 20140062940A1
• Filed: 11/16/2012
• Published: 03/06/2014
• Est. Priority Date: 08/31/2012
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Al-Dahle, Ahmad, Bi, Yafei, Ghaderi, Mir B.
• Granted Patent: US 9,201,549 B2
• Time in Patent Office: Days
• US Class Current: 345/174
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/04164 Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
• CPC Class Codes: G06F 3/04184 Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally
• CPC Class Codes: G06F 3/044 by capacitive means
• CPC Class Codes: G09G 3/36 using liquid crystals

Abstract

Systems and methods for monitoring internal resistance of a display may include supplying the display via a capacitor with a first voltage and a second voltage configured to enable the display to receive touch inputs and display image data, respectively. The method may discharge the capacitor at least three times via a first resistor, a second resistor, and the first resistor and second resistor coupled in parallel with each other. The method may monitor three discharge waveforms that corresponds to when the capacitor discharges from the first voltage to the second voltage via the first resistor, the second resistor, and the first resistor and second resistor coupled in parallel with each other. Based at least in part on the discharge waveforms, the method may determine a chip on glass resistance value and a flex on glass resistance value that correspond to an internal resistance of the display.

Claims

1. A display driver circuit comprising:

a capacitor configured to provide a plurality of voltages to a display via a supply rail, wherein the capacitor is coupled in series with a chip on glass (COG) circuit and a flex on glass (FOG) circuit of the display;

a plurality of resistors, wherein each of the plurality of resistors has substantially the same resistance value and wherein at least one of the plurality of resistors is associated with a matching error;

a plurality of switches configured to couple to the plurality of resistors, wherein each switch is configured to couple the capacitor to ground via a respective resistor of the plurality of resistors when closed; and

an interface configured to communicate with a processor, wherein the interface is configured to measure a sum of a COG resistance value and a FOG resistance value by;

closing a first switch of the plurality of switches, thereby discharging the capacitor via a first resistor;

measuring a first amount of time between when the capacitor has a first voltage value and when the capacitor discharges to a second voltage value via the first resistor;

opening the first switch after the capacitor discharges to the second voltage value;

closing a second switch of the plurality of switches, thereby discharging the capacitor via a second resistor;

measuring a second amount of time that corresponds to an amount of time between when the capacitor has the first voltage value and when the capacitor discharges to the second voltage value via the second resistor;

simultaneously closing the first switch and the second switch;

measuring a third amount of time that corresponds to an amount of time between when the capacitor has the first voltage value and when the capacitor discharges to the second voltage value via the first resistor and the second resistor; and

determining the sum of the COG resistance value and the FOG resistance value based at least in part on the first amount of time, the second amount of time, the third amount of time, and the matching error.

2. The display driver circuit of claim 1, wherein the first voltage value corresponds to a voltage value configured to enable the display to receive one or more touch inputs.

3. The display driver circuit of claim 1, wherein the second voltage value corresponds to a voltage value configured to enable the display to display image data.

4. The display driver circuit of claim 1, comprising:

a comparator circuit configured to switch states when the capacitor reaches the second voltage value; and

a timer circuit configured to measure the first, second, and third amounts of time based at least in part on when the comparator circuit switches states and a clock input.

5. The display driver circuit of claim 4, wherein the timer circuit is coupled to the plurality of switches and is configured to open the first switch when the capacitor discharges to the second voltage value.

6. The display driver circuit of claim 1, wherein the interface is configured to measure the sum of the COG resistance value and the FOG resistance value periodically.

7. The display driver circuit of claim 6, wherein the interface is configured to:

store each sum of the COG resistance value and the FOG resistance value in a log; and

send the log to a server.

8. The display driver circuit of claim 1, wherein the interface is configured to determine the sum of the COG resistance value and the FOG resistance value based on:

t₁=[R_COG+R_FOG+R]*C*ln(V₀/V₁)

t₂=[R_COG+R_FOG+R*(1+ε

)]*C*ln(V₀/V₁)

T2=[R_COG+R_FOG+0.5*R*(1+ε

)/(1+ε

/2)]*C*ln(V₀/V₁)]

wherein R_COG+R_FOG corresponds to the sum of the COG resistance value and the FOG resistance value, R corresponds to a resistance value of the first resistor and the second resistor, t₁ corresponds to the first amount of time, t₂ corresponds to the second amount of time, T2 corresponds to the third amount of time, C corresponds to a capacitance value of the capacitor, V₀ corresponds to the first voltage value, V₁ corresponds to the second voltage value, and ε

corresponds to the matching error.

9. A system comprising:

a display configured to display image data and receive one or more touch inputs;

a capacitor configured to provide a plurality of voltages to the display via a supply rail, wherein the supply rail couples the capacitor in series with an internal resistance of the display;

a plurality of switches having a plurality of resistance values, wherein each resistance value is substantially similar, wherein at least one of the plurality of switches is associated with a matching error, and wherein each switch is configured to couple the capacitor to ground when closed; and

a controller configured to measure an internal resistance value of the display by;

closing a first switch of the plurality of switches, thereby discharging the capacitor;

measuring a first amount of time between when the capacitor has a first voltage value and when the capacitor discharges to a second voltage value via the first switch;

opening the first switch after the capacitor discharges to the second voltage value;

closing a second switch of the plurality of switches;

measuring a second amount of time between when the capacitor has the first voltage value and when the capacitor discharges to a third voltage value via the second switch; and

opening the second switch after the capacitor discharges to the second voltage value;

simultaneously closing the first switch and the second switch;

measuring a third amount of time between when the capacitor has the first voltage value and when the capacitor discharges to the second voltage value via the first switch and the second switch; and

determining the internal resistance value based at least in part on the first amount of time, the second amount of time, the third amount of time, and the matching error.

10. The system of claim 9, comprising a comparator circuit coupled to the supply rail via a first resistor and to a voltage source via a second resistor, wherein the comparator circuit switches states when the capacitor discharges to the second voltage value.

11. The system of claim 9, wherein the controller is configured to acquire a plurality of measurements of the internal resistance a plurality of times.

12. The system of claim 11, wherein one or more changes in the plurality of measurements of the internal resistance corresponds to a decreased quality of the display.

13. The system of claim 9, wherein the controller is configured to measure the internal resistance value based on:

t₁=[R_COG+R_FOG+R]*C*ln(V₀/V₁)

t₂=[R_COG+R_FOG+R*(1+ε

)]*C*ln(V₀/V₁)

T2=[R_COG+R_FOG+0.5*R*(1+ε

)/(1+ε

/2)]*C*ln(V₀/V₁)]

wherein R_COG+R_FOG corresponds to the internal resistance value, R corresponds to a resistance value of the first switch and the second switch, t₁ corresponds to the first amount of time, t₂ corresponds to the second amount of time, T2 corresponds to the third amount of time, C corresponds to a capacitance value of the capacitor, V₀ corresponds to the first voltage value, V₁ corresponds to the second voltage value, and ε

corresponds to the matching error.

14. An electronic device comprising:

a display configured to display image data and receive one or more touch inputs;

a capacitor configured to provide a plurality of voltages to the display via a supply rail, wherein the supply rail couples the capacitor in series with chip on glass (COG) resistance and a flex on glass (FOG) resistance of the display;

a plurality of resistors, wherein each of the plurality of resistors has a different resistance value and wherein at least one of the plurality of resistors is associated with a matching error;

a plurality of switches configured to couple the plurality of resistors, wherein each switch is configured to couple the capacitor to ground via a respective resistor of the plurality of resistors when closed;

a comparator circuit coupled to the capacitor via a first resistor and to a reference voltage source via a second resistor; and

a processor configured to measure a sum of a COG resistance value and a FOG resistance value of the display by;

closing a first switch of the plurality of switches, thereby discharging the capacitor via a first resistor;

measuring a first amount of time between when the comparator circuit changes states, wherein the comparator circuit changes states after the capacitor discharges from a first voltage value to a second voltage value;

opening the first switch after the capacitor discharges to the second voltage value;

closing a second switch of the plurality of switches, thereby discharging the capacitor via a second resistor;

measuring a second amount of time between when the comparator circuit changes states;

determining the sum of the COG resistance and the FOG resistance values based at least in part on the first amount of time, the second amount of time, and the matching error.

15. The electronic device of claim 14, wherein the processor is configured to determine the sum of the COG resistance and the FOG resistance values based on:

R_COG+R_FOG=−

R+t₁/[C*ln(V₀/V₁)]; and

R_COG+R_FOG=−

(X)*R*(1+ε

)+t₂/[C*ln(V₀/V₁)]

wherein R_COG+R_FOG corresponds to the sum of the COG resistance value and the FOG resistance value, R corresponds to a resistance value of the first resistor, X corresponds to a ratio of a resistance value of the second resistor to the resistance value of the first resistor, t₁ corresponds to the first amount of time, t₂ corresponds to the second amount of time, C corresponds to a capacitance value of the capacitor, V₀ corresponds to the first voltage value, V1 corresponds to the second voltage value, and ε

corresponds to the matching error.

16. The electronic device of claim 14, wherein the matching error is based at least in part on an arrangement of the first resistor with respect to the second resistor.

17. A liquid crystal display (LCD), comprising:

a display driver circuit configured to provide the LCD with a plurality of voltages via a supply rail, wherein the display driver circuit comprises;

a capacitor configured to provide a plurality of voltages to a display via a supply rail, wherein the capacitor is coupled in series with a chip on glass (COG) circuit and a flex on glass (FOG) circuit of the LCD;

a plurality of resistors, wherein each of the plurality of resistors has substantially the same resistance value and wherein at least one of the plurality of resistors is associated with a matching error;

a plurality of switches configured to couple to the plurality of resistors, wherein each switch is configured to couple the capacitor to ground via a respective resistor of the plurality of resistors when closed; and

a processor configured to measure a sum of a COG resistance value and a FOG resistance value based at least in part on a first discharge waveform acquired after closing a first switch of the plurality of switches, a second discharge waveform acquired after closing a second switch of the plurality of switches, a third discharge waveform acquired after simultaneously closing the first switch and the second switch, and the matching error.

18. The LCD of claim 17, wherein the processor is configured acquire the first discharge waveform by:

closing a first switch of the plurality of switches, thereby discharging the capacitor via a first resistor;

measuring a first amount of time between when the capacitor has a first voltage value and when the capacitor discharges to a second voltage value via the first resistor; and

opening the first switch after the capacitor discharges to the second voltage value.

19. The LCD of claim 17, wherein the processor is configured acquire the second discharge waveform by:

closing a second switch of the plurality of switches, thereby discharging the capacitor via a second resistor;

measuring a second amount of time between when the capacitor has the first voltage value and when the capacitor discharges to the second voltage value via the second resistor; and

opening the second switch after the capacitor discharges to the second voltage value.

20. The LCD of claim 17, wherein the processor is configured acquire the third discharge waveform by:

simultaneously closing the first switch and the second switch, thereby discharging the capacitor via the first resistor and the second resistor;

measuring a third amount of time between when the capacitor has the first voltage value and when the capacitor discharges to the second voltage value via the first resistor and the second resistor; and

opening the first switch and the second switch after the capacitor discharges to the second voltage value.