SEMAPHORE SOFT AND HARD HYBRID ARCHITECTURE

• US 20140064271A1
• Filed: 08/22/2013
• Published: 03/06/2014
• Est. Priority Date: 08/29/2012
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Boden, Kurt Thomas
• Granted Patent: US 9,525,621 B2
• Time in Patent Office: Days
• US Class Current: 370/389
• CPC Class Codes: H04L 45/00 Routing or path finding of packets in data switching networks routing or path finding in wireless networks H04W40/00
• CPC Class Codes: H04L 45/121 by minimising delays
• CPC Class Codes: H04L 45/44 Distributed routing
• CPC Class Codes: H04L 49/00 Packet switching elements

Abstract

A packet processing device has a plurality of processing stages, including a first processing stage and a second processing stage arranged as a packet processing pipeline. The first processing stage and the second processing stage each have a respective processor configured to process a packet of a packet stream and a respective resource manager having a respective local resource lock corresponding to a remote resource. The respective processor requests the respective resource manager to allocate the remote resource. The respective resource manager responds to the request to allocate the remote resource by locking the remote resource with the respective local resource lock and allocating the remote resource. The respective processor implements a packet processing operation associated with the allocated remote resource.

Claims

1. A packet processing device comprising:

a plurality of processing stages, including a first processing stage and a second processing stage arranged as a packet processing pipeline;

the first processing stage and the second processing stage each comprising;

a respective processor configured to process a packet of a packet stream, and

a respective resource manager having a respective local resource lock corresponding to a remote resource;

the respective processor being further configured to request the respective resource manager to allocate the remote resource;

the respective resource manager being further configured to respond to the request to allocate the remote resource by locking the remote resource with the respective local resource lock and allocating the remote resource;

the respective processor being further configured to implement a packet processing operation associated with the allocated remote resource.

2. The packet processing device according to claim 1, wherein the first processing stage and the second processing stage are further configured to perform the packet processing operation, in association with the allocated remote resource, before passing the packet to a next one of the plurality of processing stages along the processing pipeline.

3. The packet processing device according to claim 1, further comprising:

a resource release bus connected to the plurality of processing stages; and

the respective resource manager being further configured to;

send to upstream ones of the plurality of processing stages a release request message; and

release the remote resource with the respective local resource lock in response to receiving the release request message.

4. The packet processing device according to claim 2, wherein the respective resource manager is further configured to:

send a release request message comprising identifiers for an identified resource manager and for an identified resource lock.

5. The packet processing device according to claim 2, wherein the respective resource manager is further configured to:

receive a release request message comprising identifiers for an identified resource manager and an identified resource lock.

6. The packet processing device according to claim 1, wherein the respective resource manager is further configured to:

detect when the remote resource cannot be locked; and

pause implementation of the packet processing operation until the remote resource is locked.

7. The packet processing device according to claim 1, further comprising the plurality of processing stages being connected in series within a same integrated circuit.

8. A packet processing device, comprising:

a plurality of processing stages arranged as a packet processing pipeline;

the processing stages each having processor cores and buffers;

the processor cores and buffers of the processing stages defining a plurality of paths, for simultaneous packet processing, through the packet processing pipeline;

an ingress front end configured to direct each packet of an incoming stream of packets into one of the plurality of paths;

the plurality of paths including a hard path and a soft path, the hard path being configured to process received ones of the incoming stream of packets with fixed latency, the soft path being configured to process received ones of the incoming stream of packets with variable latency; and

the processing stages each further including a respective resource manager configured to request allocation of a remote resource, for a given packet of the incoming stream of packets in the soft path, in response to an instruction from one of the processor cores, whereby the remote resource is allocated for processing of only the given packet.

9. The packet processing device as set forth in claim 8, further comprising the respective resource manager requesting allocation of the remote resource by referring to a semaphore locally available in the one of the plurality of processing stages in which the respective resource manager is included.

10. The packet processing device as set forth in claim 8, further comprising:

a semaphore engine storing a plurality of semaphores, each corresponding to one of a plurality of remote resources; and

the respective resource manager requesting allocation of one of the plurality of remote resources by referring to a semaphore controlled by the semaphore engine.

11. The packet processing device as set forth in claim 8, further comprising:

a plurality of engines configured to interface each said respective resource manager with one of a plurality of remote resources; and

the respective resource manager requesting allocation of one of the plurality of remote resources by referring to a semaphore controlled by one of the plurality of engines.

12. A packet processing method, for a processing stage of a pipeline packet processing device, comprising:

receiving, at a processor of a first processing stage, a first packet and a request for allocation of a remote resource;

responding, by the processor, to the allocation request, by setting a semaphore corresponding to the remote resource to indicate a locked status;

implementing a first packet processing operation, in association with the allocated remote resource, and in association with the first packet, to obtain a processed first packet; and

outputting the processed first packet to a next processing stage of the pipeline packet processing device.

13. The method of claim 12, further comprising:

receiving a second packet and an indication of an allocation of a remote resource;

implementing a second packet processing operation, associated with the allocated remote resource, on the second packet, to obtain a second processed packet;

requesting the release of the remote resource; and

outputting the second processed packet to a next processing stage of the pipeline packet processing device.

14. The method of claim 12, further comprising outputting a remote resource release indication to an upstream processing stage of the pipeline packet processing device in response to a completion of the second packet processing operation associated with the allocated remote resource.

15. The method of claim 12, further comprising obtaining the indication of the allocation of the remote resource from an execution context received together with the processed first packet.

16. A packet processing device comprising:

a plurality of processing stages, arranged as a packet processing pipeline, configured to process packets in a first direction along the packet processing pipeline;

a lock release message path connecting the plurality of processing stages, configured to communicate along a second direction opposite to said first direction;

each of the plurality of processing stages including;

a respective local resource lock, and

a respective processor core; and

the respective processor core being configured to send, along the lock release message path, a resource lock release request message identifying one of the plurality of processing stages and identifying a resource to be released.

17. The packet processing device as set forth in claim 16, further comprising a local lock buffer configured to buffer a packet when the respective local resource lock indicates that a corresponding resource is not unlocked.

18. The packet processing device as set forth in claim 16, wherein each of the plurality of processing stages further comprises a plurality of processor cores, the processor cores and buffers of the plurality of processing stages defining a plurality of paths, for simultaneous packet processing, through the packet processing pipeline.

19. The packet processing device as set forth in claim 18, further comprising an ingress front end configured to direct each of the packets into one of the plurality of paths.

20. The packet processing device as set forth in claim 19, further comprising the plurality of paths being configured as a hard path and a soft path, the hard path being configured to process received ones of the packets with fixed latency, and the soft path being configured to process received ones of the packets with variable latency, the ingress front end directing a packet requiring a remote resource to only the soft path.