System and Method for Adjusting the Sensitivity of a Capacitive Signal Source

• US 20140064523A1
• Filed: 08/30/2012
• Published: 03/06/2014
• Est. Priority Date: 08/30/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Kropfitsch, Michael, Wiesbauer, Andreas
• Granted Patent: US 9,214,911 B2
• Time in Patent Office: Days
• US Class Current: 381/174
• CPC Class Codes: H03F 2200/03 the amplifier being designed for audio applications
• CPC Class Codes: H03F 3/181 Low-frequency amplifiers, e.g. audio preamplifiers
• CPC Class Codes: H03G 1/0094 using switched capacitors
• CPC Class Codes: H03G 3/3026 the gain being discontinuously variable, e.g. controlled by switching

Abstract

In accordance with an embodiment, a system for amplifying a signal provided by a capacitive signal source includes an impedance converter having an input node configured to be coupled to a first terminal of the capacitive signal source, and an adjustable capacitive network having a first node configured to be coupled to a second terminal of the capacitive signal source and a second node coupled to an output node of the impedance converter.

Claims

1. A system for amplifying a signal provided by a capacitive signal source, the system comprising:

an impedance converter having an input node configured to be coupled to a first terminal of the capacitive signal source; and

an adjustable capacitive network having a first node configured to be coupled to a second terminal of the capacitive signal source and a second node coupled to an output node of the impedance converter.

2. The system of claim 1, wherein the adjustable capacitive network comprises:

a first capacitor coupled between the first node and the second node, and

a second capacitor coupled between the first node and a reference node, wherein at least one capacitor of the first capacitor and the second capacitor comprises an adjustable capacitor.

3. The system of claim 2, wherein the second node is a ground node.

4. The system of claim 2, wherein the adjustable capacitor comprises a plurality of capacitors selectively coupled in parallel via a corresponding plurality of switches.

5. The system of claim 4, wherein each of the plurality of capacitors comprises a top plate coupled to the first node of the capacitive network.

6. The system of claim 1, further comprising a gain control circuit configured to measure an amplitude of a signal at the output node of the impedance converter and adjust a capacitance of the capacitive network based on the measured amplitude.

7. The system of claim 1, further comprising a calibration circuit coupled to the adjustable capacitive network, wherein the calibration circuit configured to adjust a capacitance of the adjustable capacitive network.

8. The system of claim 7, wherein the calibration circuit is further configured to:

increase a bias voltage configured to be coupled to the capacitive signal source until a voltage glitch is detected from the capacitive signal source to determine a first voltage;

determine a final DC bias voltage based on the first voltage; and

apply the determined final DC bias voltage to the capacitive signal source.

9. The system of claim 7, wherein the calibration circuit comprises a lookup table circuit.

10. The system of claim 7, wherein the calibration circuit comprises memory cells configured to store a calibration setting.

11. The system of claim 1, further comprising the capacitive signal source.

12. The system of claim 11, wherein the capacitive signal source is a MEMS microphone.

13. An integrated circuit comprising:

a voltage buffer having an input node configured to be coupled to a first terminal of a MEMS microphone; and

an adjustable capacitive network having a first node configured to be coupled to a second terminal of the MEMS microphone, a second node coupled to an output node of the voltage buffer, an adjustment input configured to adjust a capacitance of the adjustable capacitive network.

14. The integrated circuit of claim 13, further comprising a gain control circuit having an input node coupled to an output of the voltage buffer and an output coupled to the adjustment input of the adjustable capacitive network, the gain control circuit configured to measure an amplitude of a signal at the output of the voltage buffer and adjust the capacitance of the capacitive network based on the measured amplitude.

15. The integrated circuit of claim 13, wherein the voltage buffer comprises a MOS source follower.

16. The integrated circuit of claim 13, wherein the voltage buffer comprises a voltage gain of 1 or less.

17. The integrated circuit of claim 13, wherein the adjustable capacitive network comprises a first capacitor array comprising:

a plurality of first capacitors having first plates coupled to the first node of the adjustable capacitive network; and

a corresponding plurality of switches coupled to second plates of the first plurality of capacitors.

18. The integrated circuit of claim 17, wherein the first plates of the plurality of first capacitors comprise top plates of the plurality of first capacitors.

19. The integrated circuit of claim 13, wherein the adjustable capacitive network comprises:

a first adjustable capacitor coupled between the first node of the adjustable capacitive network and the second node of the adjustable capacitive network; and

a second adjustable capacitor coupled between the first node of the adjustable capacitive network and a reference node.

20. The integrated circuit of claim 13, the adjustable capacitive network comprises a plurality of capacitors, each having a top plate coupled to the first node of the adjustable capacitive network, and bottom plate, wherein the bottom plate of each of the plurality of capacitors is configured to be switchably coupled to a reference node and to the second node of the adjustable capacitive network.

21. The integrated circuit of claim 13, further comprising the MEMS microphone.

22. The integrated circuit of claim 13, further comprising an analog-to-digital converter coupled to the output of the voltage buffer.

23. A method of calibrating a MEMS microphone having a first node coupled to voltage buffer circuit, the method comprising:

applying an acoustic signal to the MEMS microphone;

measuring a sensitivity of the MEMS microphone and the voltage buffer circuit; and

correcting a gain of the MEMS microphone and the voltage buffer circuit, correcting the gain comprising adjusting a capacitance of a capacitive network coupled between an output of the voltage buffer circuit and a second node of the MEMS microphone.

24. The method of claim 23, further comprising determining a difference between the measured sensitivity of the MEMS microphone and the voltage buffer circuit and a target output sensitivity.

25. The method of claim 23, wherein correcting the gain comprises selecting a switching configuration of a switchable capacitor array disposed within the capacitive network.

26. The method of claim 25, wherein selecting a switching configuration comprises configuring a digital lookup table.

27. The method of claim 23, further comprising:

increasing a bias voltage configured to be coupled to the MEMS microphone until a voltage glitch is detected from the MEMS microphone to determine a first voltage;

determining a final DC bias voltage based on the first voltage; and

applying the determined final DC bias voltage to the MEMS microphone.