Method Of Making A Low Stress Cavity Package For Back Side Illuminated Image Sensor

• US 20140065755A1
• Filed: 11/14/2013
• Published: 03/06/2014
• Est. Priority Date: 07/19/2011
• Status: Active Grant

• Current Assignee: Optiz, Inc.
• Original Assignee: Optiz, Inc.
• Inventors: Oganesian, Vage
• Granted Patent: US 8,895,344 B2
• Time in Patent Office: Days
• US Class Current: 438/65
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14683 Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 27/14685 Process for coatings or optical elements
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

An image sensor package includes an image sensor chip and crystalline handler. The image sensor chip includes a substrate, and a plurality of photo detectors and contact pads at the front surface of the substrate. The crystalline handler includes opposing first and second surfaces, and a cavity formed into the first surface. A compliant dielectric material is disposed in the cavity. The image sensor front surface is attached to the crystalline substrate handler second surface. A plurality of electrical interconnects each include a hole aligned with one of the contact pads, with a first portion extending from the second surface to the cavity and a second portion extending through the compliant dielectric material, a layer of insulation material formed along a sidewall of the first portion of the hole, and conductive material extending through the first and second portions of the hole and electrically coupled to the one contact pad.

Claims

1. A method of forming an image sensor package, comprising:

providing an image sensor chip that includes a substrate with front and back opposing surfaces, a plurality of photo detectors formed at the front surface, and a plurality of contact pads formed at the front surface which are electrically coupled to the photo detectors;

providing a crystalline handler having opposing first and second surfaces;

attaching the image sensor chip substrate front surface to the crystalline handler second surface;

forming a cavity into the first surface;

forming a compliant dielectric material in the cavity;

forming a plurality of electrical interconnects, each formed by;

forming a hole with a first portion extending from the second surface to the cavity and a second portion extending through the compliant dielectric material, wherein the hole is aligned with one of the contact pads,

forming a layer of insulation material along a sidewall of the first portion of the hole, and

forming conductive material that extends through the first and second portions of the hole, wherein the conductive material is electrically coupled to the one contact pad.

2. The method of claim 1, wherein the attaching is performed before the forming of the cavity.

3. The method of claim 1, wherein the compliant dielectric material includes a polymer.

4. The method of claim 1, wherein for each of the plurality of electrical interconnects, the hole is formed using a laser.

5. The method of claim 1, wherein for each of the plurality of electrical interconnects, the hole is tapered such that the hole has a larger cross-sectional dimension in the compliant material than at the second surface.

6. The method of claim 1, wherein for each of the plurality of electrical interconnects, a sidewall of the hole extends in a direction between 5°

and 45°

relative to a direction that is perpendicular to the first and second surfaces.

7. The method of claim 1, wherein for each of the plurality of electrical interconnects, the conductive material comprises a layer of metal extending along sidewalls of the first and second hole portions.

8. The method of claim 7, wherein for each of the plurality of electrical interconnects, the conductive material is formed using a metal plating process.

9. The method of claim 1, wherein the formation of each of the plurality of electrical interconnects further comprises:

forming a rounded interconnect disposed over the first surface and electrically coupled to the conductive material.

10. The method of claim 1, further comprising:

attaching a plurality of optical elements at the back surface for filtering and focusing light incident on the back surface, wherein the photo detectors are configured to receive light passing through the optical elements and the substrate.

11. The method of claim 1, further comprising:

attaching a glass cover to the back surface that extends over the optical elements.

12. The method of claim 1, wherein the compliant dielectric material completely fills the cavity.

13. The method of claim 1, further comprising:

forming a second cavity in the dielectric material; and

inserting a processor IC chip in the second cavity, wherein the processor IC chip is configured to process signals from the image sensor chip and includes a plurality of contact pads.

14. The method of claim 13, further comprising:

forming a second layer of insulation material that extends over the processor IC chip and the first surface; and

forming a plurality of holes each extending through the second layer of insulation material exposing one of the contact pads of the processor IC chip.

15. The method of claim 14, further comprising:

forming a plurality of rounded interconnects each disposed over and electrically coupled to one of the contact pads of the processor IC chip.