CHIP CARD COMMUNICATION ARRANGEMENT AND CHIP CARD COMMUNICATION CIRCUIT

• US 20140065981A1
• Filed: 09/04/2012
• Published: 03/06/2014
• Est. Priority Date: 09/04/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Sbuell, Richard, Kargl, Walter, Emsenhuber, Matthias
• Granted Patent: US 8,965,280 B2
• Time in Patent Office: Days
• US Class Current: 455/77
• CPC Class Codes: H03H 2/005 Coupling circuits between transmission lines or antennas and transmitters, receivers or amplifiers
• CPC Class Codes: H03H 7/004 Capacitive coupling circuits not otherwise provided for
• CPC Class Codes: H03H 7/38 Impedance-matching networks

Abstract

According to an embodiment, a chip card communication arrangement is provided comprising a matching network and a chip card communication circuit comprising at least one matching network terminal, a receiver coupled to the matching network via the at least one matching network terminal and an active transmitter coupled to the matching network via the at least one matching network terminal.

Claims

1. A chip card communication arrangement comprising:

a matching network; and

a chip card communication circuit comprising

at least one matching network terminal;

a receiver coupled to the matching network via the at least one matching network terminal; and

an active transmitter coupled to the matching network via the at least one matching network terminal.

2. Chip card communication arrangement according to claim 1, comprising a first matching network terminal and a second matching network terminal, wherein the receiver is coupled to the matching network via the first matching network terminal and the second matching network terminal and the active transmitter is coupled to the matching network via the first matching network terminal and the second matching network terminal.

3. Chip card communication arrangement according to claim 2, wherein the matching network is configured such that its input impedance at the first matching network terminal and the second matching terminal matches the output impedance at the first output terminal and the second output terminal of the transmitter.

4. Chip card communication arrangement according to claim 2, wherein the receiver comprises a first input terminal coupled to the first matching network terminal and a second input coupled to the second matching network terminal.

5. Chip card communication arrangement according to claim 2, wherein the active transmitter comprises a first output terminal coupled to the first matching network terminal and a second output terminal coupled to the second matching network terminal.

6. Chip card communication arrangement according to claim 1, further comprising an antenna coupled to the matching network.

7. Chip card communication arrangement according to claim 6, wherein the antenna is coupled to the matching network such that the receiver and the transmitter are coupled to the antenna via the matching network.

8. Chip card communication arrangement according to claim 1, wherein the matching network comprises a first capacitor coupled in parallel to the antenna and a second capacitor coupled serially between the antenna and the at least one matching network terminal.

9. Chip card communication arrangement according to claim 2, wherein the second capacitor is coupled serially between the antenna and the first matching network terminal and the matching network comprises a third capacitor coupled serially between the antenna and the second matching network terminal.

10. Chip card communication arrangement according to claim 1, wherein the chip card communication circuit is arranged on a chip card.

11. Chip card communication arrangement according to claim 10, wherein the matching network is arranged on the chip card.

12. Chip card communication arrangement according to claim 10, further comprising an antenna wherein the antenna is arranged on the chip card.

13. Chip card communication arrangement according to claim 10, wherein the chip card is a dual interface card.

14. Chip card communication arrangement according to claim 11, wherein the active transmitter comprises a differential driver.

15. Chip card communication arrangement according to claim 1, further comprising a digital signal source coupled to an input of the transmitter and configured to supply a signal to be transmitted to the transmitter.

16. Chip card communication arrangement according to claim 1, further comprising a demodulator coupled to the receiver and configured to demodulate a signal received by the receiver.

17. Chip card communication arrangement according to claim 1, wherein the receiver comprises a control loop configured to generate a peak voltage controlled signal from a signal supplied by the matching network to the receiver.

18. A chip card communication circuit comprising

at least one matching network terminal;

a receiver;

an active transmitter; and

a controller configured to, depending on the value of a control signal, couple either the receiver to the at least one matching network terminal to receive signals from the at least one matching terminal or the transmitter to the at least one matching network terminal to transmit signals to the at least one matching terminal.

19. The chip card communication circuit according to claim 18,

wherein the controller is configured to receive the control signal.

20. The chip card communication circuit according to claim 18,

wherein the control signal indicates a transmission mode or a reception mode and the controller configured to couple the receiver to the at least one matching network terminal to receive signals from the at least one matching terminal in case that the control signal indicates a reception mode and to couple the transmitter to the at least one matching network terminal to transmit signals to the at least one matching terminal in case that the control signal indicates a transmission mode.