DATAPATH CIRCUIT FOR DIGITAL SIGNAL PROCESSORS

• US 20140067889A1
• Filed: 08/27/2013
• Published: 03/06/2014
• Est. Priority Date: 09/04/2012
• Status: Active Grant

• Current Assignee: Analog Devices International Unlimited Company (Analog Devices, Inc.)
• Original Assignee: Analog Devices A/S (Analog Devices, Inc.)
• Inventors: MORTENSEN, Mikael M.
• Granted Patent: US 9,753,695 B2
• Time in Patent Office: Days
• US Class Current: 708/201
• CPC Class Codes: G06F 1/035 Reduction of table size G06F1/0314 takes precedence
• CPC Class Codes: G06F 2101/08 Powers or roots
• CPC Class Codes: G06F 2101/10 Logarithmic or exponential functions
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence
• CPC Class Codes: G06F 7/60 Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations , e.g. using difunction pulse trains, STEELE computers, phase computers conversion of digital data to or from non-denominational form H03M5/00, H03M7/00

Abstract

A datapath circuit may include a digital multiply and accumulate circuit (MAC) and a digital hardware calculator for parallel computation. The digital hardware calculator and the MAC may be coupled to an input memory element for receipt of input operands. The MAC may include a digital multiplier structure with partial product generators coupled to an adder to multiply a first and second input operands and generate a multiplication result. The digital hardware calculator may include a first look-up table coupled between a calculator input and a calculator output register. The first look-up table may include table entry values mapped to corresponding math function results in accordance with a first predetermined mathematical function. The digital hardware calculator may be configured to calculate, based on the first look-up table, a computationally hard mathematical function such as a logarithm function, an exponential function, a division function and a square root function.

Claims

1. A datapath circuit for a Digital Signal Processor, comprising:

an input memory element for storage of a first and a second input operand,

a digital multiply and accumulate circuit and a digital hardware calculator configured for parallel computation;

the digital multiply and accumulate circuit comprising;

a first input and a second input connected both to the input memory element for receipt of the first and second input operands, respectively,

a plurality of partial product generators, configured for generation of a plurality of partial products of the first or second input operands,

an adder structure configured to receive and combine the plurality of partial products to produce a multiplication result,

an arithmetic logic unit configured for receipt of the multiplication result and addition of a first variable thereto to compute an accumulated multiplication result,

a first accumulator coupled to the arithmetic logic unit and configured for receipt and manipulation of the accumulated multiplication result;

the digital hardware calculator comprising a calculator input connected to one of the first and second input operands and a calculator output register for storage of computed calculator results,

a first look-up table operatively coupled between the calculator input and the calculator output register,

wherein the first look-up table comprises a plurality of table entry values mapped to a plurality of corresponding math function results in accordance with a first predetermined mathematical function.

2. A datapath circuit according to claim 1, wherein the first input operand comprises an N-bit multiplicand and the second input operand comprises an M-bit multiplier;

the plurality of partial product generators being adapted to select respective partial products of the N-bit multiplicand, where each partial product is selected from a set of partial product results computed from the N-bit multiplicand in dependence of a predetermined set of bits of the M-bit multiplier in accordance with a predetermined coding scheme;

Each of M and N representing a positive integer number.

3. A datapath circuit according to claim 1, wherein the first predetermined mathematical function is selected from a group of {a logarithm function, an exponential function, a division function, a square root function}.

4. A datapath circuit according to claim 1, wherein the first look-up table comprises N-dimensions mapping respective N−

1 pluralities of table entry values to the corresponding math function results;

wherein N is a positive integer larger than 2.

5. A datapath circuit according to claim 1, wherein the digital hardware calculator comprises an interpolator configured for:

reading first and second math function results from the first look-up table,

applying an interpolating operation to the first and second math function results to generate an interpolated mathematical function result.

6. A datapath circuit according to claim 1, wherein the first look-up table comprises one of mask programmed Read Only Memory (ROM) and a synthesizable Read Only Memory (ROM) storing the plurality of table entry values and the plurality of corresponding math function results.

7. A datapath circuit according to claim 1, wherein the look-up table comprises readable and writable memory storing the plurality of table entry values and the plurality of corresponding math function results;

thereby supporting run-time changes to the first predetermined mathematical function.

8. A datapath circuit according to claim 7, wherein the readable and writable memory comprises memory elements selected from a group of {RAM, EPROM, EEPROM, flash memory, data register}.

9. A datapath circuit according to claim 1, comprising a multiplexer configured to selectively transmitting one of the mathematical function result and the first or second input operands to the arithmetic logic unit as the first variable.

10. A datapath circuit according to claim 1, comprising:

compressor function inserted between the input memory element and the first look-up table, the compressor function configured to mapping a numerical range of compressor input values into a smaller numerical range of compressor output values;

a multiplexer configured to selectively transmit, to an input of the first look-up table, one of the first and second input operands and corresponding compressed values of one of the first and second input operands.

11. A datapath circuit according to claim 1, wherein the digital hardware calculator further comprises:

a second look-up table operatively coupled between an output of the first look-up table and the calculator output register;

the second look-up table comprising a plurality of table entry values mapped to a plurality of corresponding math function results in accordance with a second predetermined mathematical function.

12. A datapath circuit according to claim 11, wherein the digital hardware calculator is configured for computation of at least one of:

a negative Jacobian log function, min*(x, y)=Min(x, y)−

ln(1+e<sup>(−

|x−

y|</sup>) and.

a max-log function, max*=max(x, y)+ln(1+e e<sup>(−

|x−

y|</sup>));

wherein x equals the first input operand, y equals to the second input operand, the first predetermined mathematical function comprises an exponential function and the second predetermined mathematical function comprises a logarithmic function.

13. A datapath circuit according to claim 1, wherein computational cycles executed by the digital multiply and accumulate circuit at least partly overlaps in time with computational cycles executed by the digital hardware calculator.

14. A datapath circuit according to claim 2, wherein the predetermined coding scheme comprises a Booth coding scheme selected from a group of {radix-8, radix-16, radix-32, radix-64, radix-128} Booth coding.

15. A datapath circuit according to claim 1, wherein each of the first and second input operands, the plurality of table entry values, the plurality of corresponding math function results are represented in a common binary number format selected from a group of {two'"'"'s complement, signed magnitude, redundant binary signed digit, carry save}.

16. A Digital Signal Processor circuit assembly comprising:

a Digital Signal Processor comprising;

a datapath circuit according to claim 1,

a readable and writable data memory space for storing the first look-up table;

a non-volatile memory storing;

a set of executable program instructions of a digital signal processing algorithm for execution on the Digital Signal Processor,

look-up table data content comprising the plurality of table entry values and the plurality of corresponding math function results.

17. A method of generating the look-up table data for a Digital Signal Processor circuit assembly according to claim 16, the method comprising steps of:

selecting a digital signal processing algorithm for the Digital Signal Processor,

selecting a mathematical function of the digital signal processing algorithm to be tabulated,

selecting minimum, maximum table entry values and table step size values of the first look-up table,

generating the look-up table data content by computing the plurality of table entry values and the plurality of corresponding math function results based on the selected mathematical function the minimum, maximum table entry values and table step size values,

writing the look-up table data content to an address space of the non-volatile memory.