PROCESSOR, INFORMATION PROCESSING APPARATUS, AND CONTROL METHOD OF PROCESSOR

• US 20140068194A1
• Filed: 06/28/2013
• Published: 03/06/2014
• Est. Priority Date: 08/30/2012
• Status: Abandoned Application

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Hikichi, Toru, KARASHIMA, DAISUKE, ISHIMURA, NAOYA
• Application Number:
  US13/929,925
• Publication Number:
  US 20140068194A1
• Time in Patent Office: Days
• US Class Current: 711/133
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A processor is includes cache memory; an arithmetic processing section that a load request loading an object data stored at a memory to the cache memory; a cache control part patent a process corresponding to the received load request; a memory management part which requests the object data corresponding to the request from the cache control part and header information containing information indicating whether or not the object data is a latest for the memory, and receives the header information responded by the memory; and a data management part that manages a write control of the data to the cache memory, and receives the object data responded by the memory based on the request. The requested data is transmitted from the memory to the data management part held by a CPU node without being intervened by the memory management part.

Claims

1. A processor connected to a main storage unit, comprising:

a cache memory;

an arithmetic processing section that issues a load request loading an object data stored at the main storage unit to the cache memory;

a control part that performs a process corresponding to the load request received from the arithmetic processing section;

a memory management part that requests the object data corresponding to the request from the control part and header information containing information indicating whether or not the object data is a latest for the main storage unit, and receives the header information responded by the main storage unit based on the request for the main storage unit; and

a data management part that manages a write control of the data acquired by the load request to the cache memory, and receives the object data responded by the main storage unit based on the request for the main storage unit.

2. The processor according to claim 1,

wherein the memory management part requests an object data and header information for the other processor when the header information responded by the main storage unit indicates that a latest object data exists at a cache memory of the other processor, and receives the header information responded by the other processor based on the request for the other processor, and

the data management part receives the object data responded by the other processor based on the request for the other processor.

3. The processor according to claim 1,

wherein plural flags are contained in the header information, and

the data management part instructs writing of the object data corresponding to the header information to the cache memory when values of the plural flags of the header information supplied from the memory management part are in a certain combination.

4. The processor according to claim 3,

wherein the data management part includes:

a first holding part that holds the header information supplied from the memory management part;

a second holding part that holds the object data responded by the main storage unit;

a judgment circuit that judges whether or not the values of the plural flags of the header information held at the first holding part are in the certain combination; and

an output circuit that outputs the object data held at the second holding part in accordance with a judgment result at the judgment circuit.

5. The processor according to claim 1,

wherein the memory management part includes a first entry storing both the object data and the header information, and a second entry storing not the object data but the header information, and

allocates the second entry for the load request when the main storage unit connected to the processor issuing the load request has the object data requested by the load request.

6. An information processing apparatus, comprising:

a processor including;

a cache memory;

an arithmetic processing section that issues a load request loading an object data stored at a main storage unit to the cache memory;

a control part that performs a process corresponding to the load request received from the arithmetic processing section;

a memory management part that requests the object data corresponding to the request from the control part and header information containing information indicating whether or not the object data is a latest for the main storage unit, and receives the header information responded by the main storage unit based on the request for the main storage unit; and

a data management part that manages a write control of the data acquired by the load request to the cache memory, and receives the object data responded by the main storage unit based on the request for the main storage unit, and

the main storage unit that is connected to the processor, transmits the object data to the data management part of the processor for the request from the memory management part of the processor, and transmits the header information to the memory management part of the processor.

7. A control method of a processor connected to a main storage unit and having a cache memory, comprising:

issuing a load request loading an object data stored at the main storage unit to the cache memory by an arithmetic processing section included by the processor;

performing a process corresponding to the load request received from the arithmetic processing section by a control part included by the processor;

requesting the object data corresponding to the request from the control part and header information containing information indicating whether or not the object data is a latest for the main storage unit, and receiving the header information responded by the main storage unit based on the request for the main storage unit by a memory management part included by the processor; and

managing a write control of the data acquired by the load request to the cache memory and receiving the object data responded by the main storage unit based on the request for the main storage unit by a data management part included by the processor.