TRANSACTIONAL MEMORY PROXY

• US 20140068201A1
• Filed: 08/28/2013
• Published: 03/06/2014
• Est. Priority Date: 08/31/2012
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Silicon Graphics International Corporation (Hewlett-Packard Enterprise Company)
• Inventors: Fromm, Eric
• Granted Patent: US 9,208,090 B2
• Time in Patent Office: Days
• US Class Current: 711/148
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/0828 with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 9/467 Transactional memory G06F9/528 takes precedence

Abstract

Processors in a compute node offload transactional memory accesses addressing shared memory to a transactional memory agent. The transactional memory agent typically resides near the processors in a particular compute node. The transactional memory agent acts as a proxy for those processors. A first benefit of the invention includes decoupling the processor from the direct effects of remote system failures. Other benefits of the invention includes freeing the processor from having to be aware of transactional memory semantics, and allowing the processor to address a memory space larger than the processor'"'"'s native hardware addressing capabilities. The invention also enables computer system transactional capabilities to scale well beyond the transactional capabilities of those found computer systems today.

Claims

1. A method for optimizing processor performance in a compute node for transactional memory accesses, the method comprising:

allocating a transactional memory agent to one or more processors in a compute node;

performing global memory transactions for a processor in a compute node by the allocated transactional memory agent ;

copying data from one or more globally shared memory addresses identified by a transactional request for data into a private region of memory associated with a requesting processor during shared memory read operations by the transactional memory agent; and

sending data from the private region of memory associated with the requesting processor by the transactional memory agent targeting globally shared memory during a transactional memory write operation.

2. The method of claim 1, wherein the transactional memory agent is configured to handle one memory transaction with the global memory at a time

3. The method of claim 2, wherein the global memory is a globally addressable distributed memory system.

4. The method of claim 1, wherein the memory associated with the requesting processor is a private memory space exclusive to the processor.

5. The method of claim 1, further comprising:

building a memory transaction for the transactional memory agent to conduct from a combination of subcomponent memory transactions;

and initiating an atomic commit phase according to a global coherence protocol.

6. The method of claim 1, further comprising:

communicating one or more transaction conflict related probe actions to the processor;

receiving a processor response to the one or more transaction conflict related probe actions from the processor; and

generating a probe response from the processor response in accordance with a global coherence protocol.

7. The method of claim 1, further comprising including a global timestamp coupled with a unique transaction ID in each memory transaction communication from the transactional memory agent, wherein the global timestamp identifies when the overall transaction was initiated.

8. The method of claim 7, wherein a probe carries the global timestamp and the unique transaction ID associated with a transactional request.

9. The method of claim 1, wherein the transaction memory agent NACKing probe requests from a globally coherent shared memory controller based on time stamp and transaction ID comparisons, wherein the memory controller automatically retries the probe requests until they terminate with a probe completion reply.

10. The method of claim 1, further comprising providing or maintaining a reverse address translation mechanism, wherein the reverse address translation mechanism provides a mapping between globally coherent memory controller directed probes that target physical addresses, and probes that communicate with one or more virtual addresses.

11. The method of claim 1, further comprising:

receiving a command from the processor providing one or more transaction variables to be written to a globally coherent memory;

determining whether or not to write the one or more transaction variables to the globally coherent memory; and

writing the one or more transaction variables to the globally coherent memory.

12. The method of claim 10, wherein determining not to write the one or more transaction variables is based on at least one of receiving an error indicator and failing to complete the write transaction within a threshold amount of time.

13. The method of claim 11, further comprising one of retrying a failed write transaction and confirming cancellation of the failed write transaction.

14. The method of claim 1, wherein the memory transactions include transactional memory traffic and non-transactional memory traffic.

16. The non-transitory computer readable storage medium of claim 13, wherein the transactional memory agent is configured to handle one memory transaction with the global memory at a time

18. The non-transitory computer readable storage medium of claim 14, wherein the memory associated with the requesting processor is a private memory space exclusive to the processor.

19. The non-transitory computer readable storage medium of claim 14, further comprising:

building a memory transaction for the transactional memory agent to conduct from a combination of subcomponent memory transactions;

and initiating an atomic commit phase according to a global coherence protocol.

20. The non-transitory computer readable storage medium of claim 14, further comprising:

communicating one or more transaction conflict related probe actions to the processor;

receiving a processor response to the one or more transaction conflict related probe actions from the processor; and

generating a probe response from the processor response in accordance with a global coherence protocol.

21. The non-transitory computer readable storage medium of claim 14, further comprising including a global timestamp coupled with a unique transaction ID in each memory transaction communication from the transactional memory agent, wherein the global timestamp identifies when the overall transaction was initiated.

22. The non-transitory computer readable storage medium of claim 20, wherein a probe carries the global timestamp and the unique transaction ID associated with a transactional request.

23. The non-transitory computer readable storage medium of claim 14, wherein the transaction memory agent NACKing probe requests from a globally coherent shared memory controller based on time stamp and transaction ID comparisons, wherein the the memory controller automatically retry the probe requests until they terminate with a probe completion reply.

24. The non-transitory computer readable storage medium of claim 14, further comprising providing or maintaining a reverse address translation mechanism, wherein the reverse address translation mechanism provides a mapping between globally coherent memory controller directed probes that target physical addresses, and probes that communicate with one or more virtual addresses.

25. The non-transitory computer readable storage medium of claim 14, further comprising:

receiving a command from the processor providing one or more transaction variables to be written to a globally coherent memory;

determining whether or not to write the one or more transaction variables to the globally coherent memory; and

writing the one or more transaction variables to the globally coherent memory.

26. The non-transitory computer readable storage medium of claim 23, wherein determining not to write the one or more transaction variables is based on at least one of receiving an error indicator and failing to complete the write transaction within a threshold amount of time.

27. The non-transitory computer readable storage medium of claim 24, further comprising one of retrying a failed write transaction and confirming cancellation of the failed write transaction.

15. A non-transitory computer readable storage medium having embodied thereon a program executable by a processor to perform a method, the method comprising:

allocating a transactional memory agent to one or more processors in a compute node;

performing global memory transactions for a processor in a compute node by the allocated transactional memory agent ;

copying data from one or more globally shared memory addresses identified by a transactional request for data into a private region of memory associated with a requesting processor during shared memory read operations by the transactional memory agent; and

sending data from the private region of memory associated with the requesting processor by the transactional memory agent targeting globally shared memory during a transactional memory write operation.

17. The non-transitory computer readable storage medium of claim 15, wherein the global memory is a globally addressable distributed memory system.

28. A system comprising:

a plurality of compute nodes;

a memory in each of the compute nodes; and

a transactional memory agent in one or more of the compute nodes of a data center, wherein the transactional memory agent in a first compute node performs global memory transactions between a requesting processor in a compute node to coherent shared memory controller, wherein the transactional memory agent copies data from one or more shared memory addresses to private memory associated with the requesting processor during memory read operations, and wherein the transactional memory agent sends data from the private memory associated with the requesting processor targeting shared memory.