SECURITY CHIP, PROGRAM, INFORMATION PROCESSING APPARATUS, AND INFORMATION PROCESSING SYSTEM

• US 20140068280A1
• Filed: 08/20/2013
• Published: 03/06/2014
• Est. Priority Date: 09/05/2012
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Yoshimi, Hideo
• Granted Patent: US 9,158,939 B2
• Time in Patent Office: Days
• US Class Current: 713/194
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G09C 1/00 Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system cryptographic typewriters G09C3/00
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 9/0866 involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics
• CPC Class Codes: H04L 9/3271 using challenge-response

Abstract

There is provided a security chip having a tamper-resistant feature, including an acquisition part configured to acquire specific information transmitted by a device performing challenge-response authentication, the specific information being specific to the device, a storage configured to store second key information that enables generation of first key information from the specific information, the first key information being used by the device for challenge-response authentication, and a generation part configured to generate, using the second key information, the first key information from the specific information. A response to be transmitted to the device is generated, using the first key information, from a challenge transmitted by the device. In the device, the first key information is not stored in a tamper-resistant security chip.

Claims

1. A security chip having a tamper-resistant feature, comprising:

an acquisition part configured to acquire specific information transmitted by a device performing challenge-response authentication, the specific information being specific to the device;

a storage configured to store second key information that enables generation of first key information from the specific information, the first key information being used by the device for challenge-response authentication; and

a generation part configured to generate, using the second key information, the first key information from the specific information,

wherein a response to be transmitted to the device is generated, using the first key information, from a challenge transmitted by the device, and

wherein, in the device, the first key information is not stored in a tamper-resistant security chip.

2. The security chip according to claim 1,

wherein the second key information is key information shared with another security chip that operates in a same manner as the security chip.

3. The security chip according to claim 1,

wherein the specific information is information that is randomly generated for the device.

4. The security chip according to claim 1,

wherein the specific information is identification information for uniquely identifying the device or a component of the device.

5. The security chip according to claim 1,

wherein the generated first key information is stored, and

wherein, after the first key information is stored, when the specific information is acquired, the response is generated from the challenge by using the stored first key information.

6. The security chip according to claim 1,

wherein, in a case where a predetermined condition is satisfied, the generated first key information is transmitted to the device.

7. The security chip according to claim 6,

wherein the predetermined condition includes that a number of times the first key information is transmitted does not exceed a predetermined number of times.

8. The security chip according to claim 1,

wherein the challenge-response authentication includes comparing the response generated by the security chip with a response generated by the device from the challenge by using the first key information.

9. The security chip according to claim 1,

wherein transmission of the challenge and the specific information, or transmission of the response is performed using near field communication (NFC).

10. The security chip according to claim 9,

wherein the transmission of the challenge and the specific information, or the transmission of the response is performed using a command for writing or a command for reading compliant with a communication standard of the near field communication (NFC).

11. A program for causing a security chip having a tamper-resistant feature to function as

an acquisition part configured to acquire specific information transmitted by a device performing challenge-response authentication, the specific information being specific to the device, and

a generation part configured to generate first key information from the specific information using second key information stored in the security chip, the second key information enabling generation of the first key information from the specific information, the first key information being used by the device for challenge-response authentication,

wherein a response to be transmitted to the device is generated, using the first key information, from a challenge transmitted by the device, and

wherein, in the device, the first key information is not stored in a tamper-resistant security chip.

12. An information processing apparatus comprising:

a communication interface configured to receive a challenge transmitted by a device performing challenge-response authentication and specific information transmitted by the device, the specific information being specific to the device, and to transmit a response corresponding to the challenge to the device; and

a security chip having a tamper-resistant feature,

wherein the security chip includes

an acquisition part configured to acquire the specific information,

a storage configured to store second key information that enables generation of first key information from the specific information, the first key information being used by the device for challenge-response authentication, and

a generation part configured to generate, using the second key information, the first key information from the specific information,

wherein a response to be transmitted to the device is generated from the challenge by using the first key information, and

wherein, in the device, the first key information is not stored in a tamper-resistant security chip.

13. An information processing apparatus comprising:

a communication interface configured to transmit a challenge and specific information specific to the information processing apparatus, the challenge and the specific information being used for challenge-response authentication, to a device including a security chip having a tamper-resistant feature, and to receive a response corresponding to the challenge from the device; and

a processing circuit configured to perform challenge-response authentication by using first key information stored in the information processing apparatus, the challenge, and the response,

wherein the security chip stores second key information that enables generation of the first key information from the specific information,

wherein the first key information is generated by the security chip using the second key information from the specific information,

wherein, in the device, the response is generated from the challenge by using the first key information, and

wherein, in the information processing apparatus, the first key information is not stored in a tamper-resistant security chip.

14. An information processing system comprising:

a first information processing apparatus; and

a second information processing apparatus,

wherein the first information processing apparatus includes

a communication interface configured to transmit a challenge and specific information specific to the first information processing apparatus, the challenge and the specific information being used for challenge-response authentication, to the second information processing apparatus, and to receive a response corresponding to the challenge from the second information processing apparatus, and

a processing circuit configured to perform challenge-response authentication by using first key information stored in the first information processing apparatus, the challenge, and the response,

wherein the second information processing apparatus includes

a communication interface configured to receive the challenge and the specific information, the challenge and the specific information being transmitted by the first information processing apparatus, and to transmit the response to the first information processing apparatus, and

a security chip having a tamper-resistant feature,

wherein the security chip includes

an acquisition part configured to acquire the specific information,

a storage configured to store second key information that enables generation of the first key information from the specific information, and

a generation part configured to generate, using the second key information, the first key information from the specific information,

wherein, in the second information processing apparatus, the response is generated from the challenge by using the first key information, and

wherein, in the first information processing apparatus, the first key information is not stored in a tamper-resistant security chip.