SYSTEM AND PROCESS FOR ACCOUNTING FOR AGING EFFECTS IN A COMPUTING DEVICE

• US 20140068298A1
• Filed: 09/05/2012
• Published: 03/06/2014
• Est. Priority Date: 09/05/2012
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Simeral, Brad
• Granted Patent: US 9,823,990 B2
• Time in Patent Office: Days
• US Class Current: 713/322
• CPC Class Codes: G01R 31/00 Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere measuring superconductive properties G01R33/1238; testing or measuring semiconductors or solid state devices during manufacture H01L22/00; testing line transmission systems H04B3/46
• CPC Class Codes: G01R 31/2855 Environmental, reliability or burn-in testing
• CPC Class Codes: G06F 11/3003 Monitoring arrangements specially adapted to the computing system or computing system component being monitored
• CPC Class Codes: G06F 11/3058 Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations thermal management in cooling arrangements of a computing system G06F1/206
• CPC Class Codes: G06F 11/3409 for performance assessment
• CPC Class Codes: G06F 17/00 Digital computing or data processing equipment or methods, specially adapted for specific functions information retrieval, database structures or file system structures therefor G06F16/00
• CPC Class Codes: G06F 2119/04 Ageing analysis or optimisation against ageing
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30

Abstract

Embodiments of the claimed subject matter are directed to methods and systems that allow tracking and accounting of wear and other aging effects in integrated circuits and products which include integrated circuits over time, and the dynamic adjustment of operating conditions to increase or decrease wear in response to the accumulated wear relative to the expected wear during the lifetime of the circuit and/or product.

Claims

1. A method, comprising:

determining an amount of wear in a computing system over time;

calculating a number of accumulated credits for the computing device based on the determined amount of wear;

adjusting operating conditions in the computing system based on the number of accumulated credits; and

operating the computing system under adjusted operating conditions.

2. The method according to claim 1, wherein operating the computing system under adjusted operating conditions consumes accumulated credits of the computing system.

3. The method according to claim 2, wherein the computing system comprises a power supply device configured to supply power to the computing device,

further wherein adjusting the operating conditions comprises adjusting a voltage of the power supplied by the power supply device during operation.

4. The method according to claim 3, wherein adjusting the operating conditions comprises adjusting the voltage of the power supplied by the power supply device to a higher voltage or a lower voltage during operation.

5. The method according to claim 4, wherein adjusting the operating conditions comprises adjusting the voltage of the power supplied by the power supply device to a higher voltage during operation based on a remaining number of accumulated credits.

6. The method according to claim 2, wherein the computing system comprises a processor configured to operate at a frequency,

further wherein adjusting the operating conditions comprises adjusting a frequency of the processor during operation.

7. The method according to claim 6, wherein adjusting the operating conditions comprises adjusting the frequency of the processor during operation to a higher frequency or a lower frequency during operation.

8. The method according to claim 7, wherein adjusting the operating conditions comprises adjusting the frequency of the processor during operation to a higher frequency during operation based on a remaining number of accumulated credits.

9. The method according to claim 1, further comprising monitoring a junction temperature of a component comprised in the computing system during operation of the computing system

10. The method according to claim 9, wherein the junction temperature of a component comprised in the computing system is not allowed to exceed a max junction temperature corresponding to the component.

11. The method according to claim 10, wherein adjusting the operating conditions comprises adjusting the max junction temperature corresponding to a component comprised in the computing system during operation to a higher max junction temperature or a lower max junction temperature during operation.

12. The method according to claim 11, wherein adjusting the operating conditions comprises adjusting the max junction temperature corresponding to a component comprised in the computing system to a higher max junction temperature during operation based on a remaining number of accumulated credits.

13. The method according to claim 1, wherein determining an amount of wear comprises:

tracking operating conditions of the computing system;

comparing the tracked operating conditions of the computing system to a reference; and

computing a current wear in the computing system relative to the reference.

14. The method according to claim 13, wherein computing the current wear in the computing system comprises mapping the operating conditions to a wear curve.

15. The method according to claim 13, wherein the reference comprises a wear curve of a Mean Time Before Failure (MTBF) for the computing system for a worst case user.

16. The method according to claim 1, wherein the computing system comprises a plurality of circuits configured to measure a performance of a plurality of transistors and to inspect the plurality of transistors for wear over time.

17. The method according to claim 16, wherein the plurality of circuits comprises a plurality of oscillators.

18. The method according to claim 16, wherein the plurality of transistors are isolated from voltage induced age.

19. The method according to claim 18, wherein the plurality of transistors are isolated from voltage induced age by power-gating.

20. A computing system comprising:

a processor configured to process programmed instructions in the computing system at a plurality of frequencies;

a power supply device configured to supply power to the computing system at a plurality of voltages; and

a plurality of integrated circuits that accumulates wear over time during operation of the computing system,

wherein, operating conditions in the computing system and corresponding to at least one of the processor and the power supply device are adjusted based on a number of accumulated credits determined to correspond to the accumulated wear on the plurality of integrated circuits.

21. The computing system according to claim 20, wherein a voltage of the power supplied by the power supply device during operation is adjusted based on the number of accumulated credits determined to correspond to the accumulated wear on the plurality of integrated circuits.

22. The computing system according to claim 20, wherein a frequency of the processor during operation is adjusted based on the number of accumulated credits determined to correspond to the accumulated wear on the plurality of integrated circuits.

23. The computing system according to claim 20, wherein the computing system further comprises a plurality of circuits configured to measure a performance of a plurality of transistors and to inspect the plurality of transistors for accumulated wear over time, and

wherein the number of accumulated credits corresponds to wear over time accumulated by the plurality of transistors.

24. The computing system according to claim 23, wherein the plurality of transistors comprises a plurality of transistors isolated from voltage induced age.

25. The computing system according to claim 23, wherein the plurality of circuits comprises a plurality of oscillators.

26. The computing system according to claim 20, wherein the number of accumulated credits corresponding to the accumulated wear on the plurality of integrated circuits is estimated by tracking operating conditions in the computing system, comparing the tracked operating conditions in the computing system to a reference, and computing a current position of the computing system relative to the reference.

27. The computing system according to claim 20, further comprising a temperature sensor configured to measure an internal temperature of the plurality of integrated circuits comprised in the computing system.

28. The computing system according to claim 27, wherein the plurality of integrated circuits have a corresponding plurality of max junction temperatures, the plurality of max junction temperatures comprising an operating temperature of the plurality of integrated circuits not to be exceeded during operation of the computing system.

29. The computing system according to claim 28, wherein a max junction temperature of the plurality of max junction temperatures is adjusted based on the number of accumulated credits determined to correspond to the accumulated wear on the plurality of integrated circuits.

30. A computing system comprising:

a processor configured to process programmed instructions in the computing system at a plurality of frequencies;

a power supply device configured to supply power to the computing system at a plurality of voltages; and

a plurality of integrated circuits that accumulates wear over time during operation of the computing system,

wherein the computing system accumulates a plurality of operating credits while the computing system operates at a performance level under a pre-determined threshold and consumes operating credits while the computing system operates at a performance level above the pre-determined threshold,

wherein the performance level corresponds to at least one of a voltage supplied by the power supply device, a processor frequency in the computing system, and a junction temperature of a component in the computing system

further wherein, the computing system is further operable to operate at a performance level above the pre-determined threshold for so long as a surplus of the operating credits remains.

31. The computing system according to claim 30, wherein the performance level of the computing device is increased by increasing at least one of:

the voltage supplied by the power supply device, the processor frequency, and the junction temperature of a component.

32. The computing system according to claim 30, wherein the performance level of the computing device is decreased by decreasing at least one of:

the voltage supplied by the power supply device, the processor frequency, and the junction temperature of a component.

33. The computing system according to claim 30, wherein the rate at which wear is accumulated by the plurality of integrated circuits corresponds to the performance level of the computing system.

34. The computing system according to claim 33, wherein the accumulation of operating credits corresponds to an estimated level of wear accumulated by the plurality of integrated circuits relative to a reference level of wear.

35. The computing system according to claim 34, wherein the level of wear accumulated by the plurality of integrated circuits is estimated by tracking operating conditions in the computing system, comparing the tracked operating conditions in the computing system to a reference, and computing a current position of the computing system relative to the reference.

36. The computing system according to claim 33, wherein the computing system further comprises a plurality of circuits configured to measure a performance of a plurality of transistors and to inspect the plurality of transistors for accumulated wear over time.

37. The computing system according to claim 36, wherein the number of accumulated operating credits is determined by inspecting the plurality of transistors for wear over time.