Error Detection And Correction In A Memory System

• US 20140068319A1
• Filed: 09/19/2012
• Published: 03/06/2014
• Est. Priority Date: 09/06/2012
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Daly, David M.
• Application Number:
  US13/622,521
• Publication Number:
  US 20140068319A1
• Time in Patent Office: Days
• US Class Current: 714/6.2
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 2211/1088 Scrubbing in RAID systems with parity
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 2211/4062 Parity or ECC in refresh operations
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

An apparatus including at least one memory controller; and a plurality of random access memories, where the at least one memory controller is configured to allocate the plurality of random access memories among at least a first portion, a second portion and a third portion. The first portion is configured to store protected data. The second portion is configured to store parity information for the stored protected data. The third portion is configured to store unprotected data.

Claims

1. A non-transitory computer-readable storage medium, storing program instructions, execution of the program instructions resulting in operations comprising:

storing, by an apparatus, protected data on a first portion of a plurality of random access memories; and

storing, by the apparatus, parity information for the stored data on a second portion of the plurality of random access memories; and

storing unprotected data on a third region of the plurality of random access memories.

2. The non-transitory computer-readable storage medium of claim 1 where the operations further comprise dynamically varying a first amount of the protected data and a second amount of the unprotected data.

3. The non-transitory computer-readable storage medium of claim 1 where a first size of the first region and a third size of the third region are dynamically variable.

4. The non-transitory computer-readable storage medium of claim 1 where the operations further comprise allocating a total memory space of the plurality of random access memories among a group consisting of the first region, the second region and the third region.

5. The non-transitory computer-readable storage medium of claim 1 where the operations further comprise reallocating a total memory space of the plurality of random access memories among a group consisting of the first region, the second region, the third region and a fourth region of the plurality of random access memories, where the fourth region consists of a portion of the plurality of random access memories that has been determined to be inaccessible or unusable.

6. The non-transitory computer-readable storage medium of claim 1 where the operations further comprise reallocating a total memory space of the plurality of random access memories among a group consisting of the first region, the second region, the third region and a fourth region of the plurality of random access memories, where the fourth region consists of a portion of the plurality of random access memories that is inaccessible or unusable.

7. The non-transitory computer-readable storage medium of claim 1 where the first region, the second region and the third region do not overlap one another.

8. The non-transitory computer-readable storage medium of claim 1 where the operations further comprise using the parity information to reconstruct a lost or inaccessible portion of the protected data.

9. The non-transitory computer-readable storage medium of claim 1 where the operations further comprise in response to an uncorrectable error occurring for one of the plurality of random access memories, continuing usage of remaining ones of the plurality of random access memories by using the parity information to reconstruct lost or inaccessible protected data.

10. The non-transitory computer-readable storage medium of claim 1 where the parity information enables reconstruction of a portion of protected data stored on a random access memory that fails.

11. The non-transitory computer-readable storage medium of claim 1 where the operations further comprise:

writing new protected data to one of the plurality of random access memories;

computing updated parity information based on the new protected data; and

writing the updated parity information to the second region of the plurality of random access memories.

12. The non-transitory computer-readable storage medium of claim 1 where the operations further comprise:

in response to a command to write new protected data to a random access memory that has failed, reading other protected data from others of the plurality of random access memories and reading the parity information from the second region of the plurality of random access memories;

reconstructing missing protected data for the failed random access memory based on the other protected data and the parity information;

determining new parity information based on the new protected data and the reconstructed missing protected data; and

writing the new parity information to the second region of the plurality of random access memories.

13. An apparatus comprising:

at least one memory controller; and

a plurality of random access memories,

where the at least one memory controller is configured to allocate the plurality of random access memories among at least a first portion, a second portion and a third portion, where the first portion is configured to store protected data, where the second portion is configured to store parity information for the stored protected data, and where the third portion is configured to store unprotected data.

14. An apparatus as in claim 13 where the at least one memory controller is configured to dynamically vary a first amount of the protected data and a second amount of the unprotected data.

15. An apparatus as in claim 13 where the at least one memory controller is configured to allocate a total memory space of the plurality of random access memories among a group consisting of the first region, the second region and the third region.

16. An apparatus as in claim 13 where the at least one memory controller is configured to reallocate a total memory space of the plurality of random access memories among a group consisting of the first region, the second region, the third region and a fourth region of the plurality of random access memories, where the fourth region consists of a portion of the plurality of random access memories that has been determined to be inaccessible or unusable.

17. An apparatus as in claim 13 where the at least one memory controller is configured to reallocate a total memory space of the plurality of random access memories among a group consisting of the first region, the second region, the third region and a fourth region of the plurality of random access memories, where the fourth region consists of a portion of the plurality of random access memories that is inaccessible or unusable.

18. An apparatus as in claim 13 where the at least one memory controller is configured to use the parity information to reconstruct a lost or inaccessible portion of the protected data.

19. An apparatus as in claim 13 where the at least one memory controller is configured to, in response to an uncorrectable error occurring for one of the plurality of random access memories, continue usage of remaining ones of the plurality of random access memories by using the parity information to reconstruct lost or inaccessible protected data.

20. An apparatus as in claim 13 where the at least one memory controller is configured to:

write new protected data to one of the plurality of random access memories;

compute updated parity information based on the new protected data; and

write the updated parity information to the second region of the plurality of random access memories.

21. An apparatus as in claim 13 where the at least one memory controller is configured to:

in response to a command to write new protected data to a random access memory that has failed, read other protected data from others of the plurality of random access memories and reading the parity information from the second region of the plurality of random access memories;

reconstruct missing protected data for the failed random access memory based on the other protected data and the parity information;

determine new parity information based on the new protected data and the reconstructed missing protected data; and

write the new parity information to the second region of the plurality of random access memories.