ELECTRONIC APPARATUS, METHOD OF OPTIMIZING DE-COUPLING CAPACITOR AND COMPUTER-READABLE RECORDING MEDIUM

• US 20140068539A1
• Filed: 03/13/2013
• Published: 03/06/2014
• Est. Priority Date: 09/03/2012
• Status: Active Grant

• Current Assignee: HP Printing Korea Co., Ltd. (HP Inc.)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: PARK, Seung-hun, JUNG, Dong-yeol, LEE, Sang-ho, CHEON, Jeong-nam
• Granted Patent: US 8,984,471 B2
• Time in Patent Office: Days
• US Class Current: 716/115
• CPC Class Codes: G06F 2119/10 Noise analysis or noise optimisation
• CPC Class Codes: G06F 30/36 Circuit design at the analogue level
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 30/373 Design optimisation
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/19106 in a mirrored arrangement on two different side of a common die mounting substrate
• CPC Class Codes: H05K 1/0231 : Capacitors or dielectric substances
• CPC Class Codes: H05K 1/114 : Pad being close to via, but not surrounding the via
• CPC Class Codes: H05K 1/181 : associated with surface mounted components
• CPC Class Codes: H05K 2201/10053 : Switch
• CPC Class Codes: H05K 2201/10159 : Memory
• CPC Class Codes: H05K 2201/10545 : Related components mounted on both sides of the PCB
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product

Abstract

An electronic apparatus may include a circuit board, a processor disposed on an upper surface of the circuit board, and a memory disposed on a lower surface of the circuit board, such that the lower surface of the circuit board where the processor is arranged overlaps an area corresponding to where the memory is disposed.

Claims

1. An electronic apparatus, comprising:

a circuit board;

a processor disposed on an upper surface of the circuit board; and

a memory disposed on a lower surface of the circuit board,

wherein the lower surface of the circuit board on which the processor is arranged overlaps an area corresponding to where the memory is disposed.

2. The electronic apparatus of claim 1, wherein the processor comprises a plurality of first terminals to transmit and receive signals to and from the memory,

the memory comprises a plurality of second terminals to transmit and receive signals to and from the processor, and

at least one of the plurality of first terminals connects to at least one of the plurality of second terminals through a via hole of the circuit board.

3. The electronic apparatus of claim 2, wherein the plurality of first terminals are arranged on an upper surface of the circuit board, and

the plurality of second terminals are arranged on a lower surface of the circuit board to correspond to the plurality of first terminals.

4. The electronic apparatus of claim 2, wherein the signals transmitted and received through the plurality of first terminals and the plurality of second terminals comprise at least one of a data signal, a control signal and a clock signal.

5. The electronic apparatus of claim 1, further comprising:

a de-coupling capacitor commonly connected to a power supply of the processor and a power supply of the memory.

6. The electronic apparatus of claim 5, further comprising:

a first switch arranged between the power supply of the processor and the de-coupling capacitor; and

a second switch arranged between the power supply of the processor and the de-coupling capacitors, wherein

the controller shunts the first switch and opens the second switch during a memory writing operation, and

the controller opens the first switch and shunts the second switch during a memory reading operation.

7. The electronic apparatus of claim 6, wherein the processor transmits a chip select signal to the memory,

the first switch shunts if the chip select signal is on and opens if the chip select signal is off, and

the second switch opens if the chip select signal is on and shunts if the chip select signal is off.

8. The electronic apparatus of claim 5, wherein the de-coupling capacitor comprises a plurality of de-coupling capacitors connected in parallel.

9. An electronic apparatus, comprising:

a user interface to receive select input of a plurality of circuit devices;

a storage to store electrical current information and a Scattering parameter (S-parameter) regarding input/output (I/O) ports of the plurality of circuit devices respectively;

a calculator to calculate impedance per number of de-coupling capacitors based on the stored S-parameters and to calculate an accumulated noise value per number of the de-coupling capacitors based on the calculated impedance and the electrical current information; and

a controller to determine a number of the de-coupling capacitors based on the calculated accumulated noise values and to control the user interface to display the determined number of the de-coupling capacitors.

10. The electronic apparatus of claim 9, wherein the storage stores the electrical current information according to the IBIS model of the I/O ports of the plurality of circuit devices respectively.

11. The electronic apparatus of claim 9, wherein the I/O ports input and output at least one of a control signal, a data signal and an address signal of the circuit devices.

12. The electronic apparatus of claim 9, wherein the S-parameter is retrieved by utilizing the electromagnetic simulation of the Power Distribution Network (PDN) regarding the I/O ports of the plurality of circuit devices respectively.

13. The electronic apparatus of claim 9, wherein the calculator calculates a noise value per frequency bandwidth based on the calculated impedance and the electrical current information, and calculates the accumulated noise values by accumulating the calculated noise values of the frequency bandwidths.

14. The electronic apparatus of claim 9, wherein the plurality of circuit devices comprise the memory and the processor.

15. A method of optimizing de-coupling capacitors, the method comprising:

retrieving electrical current information and a Scattering parameter (S-parameter) regarding the I/O ports of a plurality of selected circuit devices respectively;

calculating impedance per number of the de-coupling capacitors based on the retrieved S-parameter and calculating an accumulated noise value per number of the de-coupling capacitors based on the calculated impedance and the retrieved electrical current information; and

determining the number of the de-coupling capacitors based on the calculated accumulated noise values.

16. The method of claim 15, wherein the retrieving comprises retrieving the electrical current information according to the IBIS model regarding the I/O ports of the plurality of circuit devices respectively.

17. The method of claim 15, wherein the I/O ports input and output at least one of a control signal, a data signal, and an address signal of the circuit devices.

18. The method of claim 15, wherein the S-parameter is retrieved by utilizing the electromagnetic simulation of the PDN regarding the I/O ports of the plurality of circuit devices respectively.

19. The method of claim 15, wherein the calculating comprises:

calculating noise value per frequency bandwidth based on the calculated impedance and the electrical current information; and

calculating accumulated noise values by accumulating the calculated noise values of the frequency bandwidths.

20. A computer-readable recording medium having recorded thereon computer-readable codes to execute a method of optimizing de-coupling capacitors, the method comprising:

retrieving electrical current information and a Scattering parameter (S-parameter) regarding the I/O ports of a plurality of selected circuit devices respectively;

calculating impedance per number of the de-coupling capacitors based on the retrieved S-parameter and calculating an accumulated noise value per number of the de-coupling capacitors based on the calculated impedance and the retrieved electrical current information; and

determining the number of the de-coupling capacitors based on the calculated accumulated noise values.

21. An electronic apparatus, comprising:

a user interface to allow a user to select a plurality of circuit devices configured to be stacked with respect to each other;

a controller to determine a number of de-coupling capacitors to be used within the electronic apparatus resulting from a calculation of accumulated noise values per number of de-coupling capacitors based on an impedance per number of de-coupling capacitors and electrical current information of the electronic apparatus; and

at least one de-coupling capacitor commonly-connected to at least two of the plurality of circuit devices to reduce noise within the electronic apparatus based on the calculation of the accumulated noise values.

22. The electronic apparatus of claim 21, wherein the controller determines a least number of the de-coupling capacitors from among the calculated accumulated noise values that does not exceed 10% of a standard accumulated noise.

23. The electronic apparatus of claim 21, wherein the plurality of circuit devices comprise at least two of a circuit board, a memory, and a processor.

24. The electronic apparatus of claim 21, wherein the electronic apparatus further comprises:

a storage to store the electrical current information and a Scattering parameter (S-parameter) regarding input/output (I/O) ports of each of the plurality of circuit devices; and

a calculator to calculate the impedance per number of the de-coupling capacitors based on the stored S-parameters and to perform the calculation of the accumulated noise value per number of the de-coupling capacitors based on the calculated impedance and the electrical current information.