Hydrogenation and Crystallization of Polycrystalline Silicon

• US 20140070225A1
• Filed: 09/06/2013
• Published: 03/13/2014
• Est. Priority Date: 09/07/2012
• Status: Abandoned Application

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Yu, Cheng-Ho, Yousefpor, Marduke, Poon, Stephen S., Chang, Ting-Kuo, Park, Young Bae, Chen, Yu-Cheng
• Application Number:
  US14/020,620
• Publication Number:
  US 20140070225A1
• Time in Patent Office: Days
• US Class Current: 257/72
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate

Abstract

A TFT stack for a liquid crystal display is provided. The TFT stack includes a silicon layer that includes a heavily doped region, a non-doped region, and a lightly doped region between the heavily doped region and the non-doped region. The heavily doped region is hydrogenated. The TFT stack also includes an insulation layer that includes a first portion formed over the lightly doped region and a second portion disposed over the non-doped region and a gate metal electrode layer formed over the second portion of the non-doped region. The TFT stack also includes a first dielectric layer disposed over the gate metal electrode and over the first portion of the insulation layer. The heavily doped region is hydrogenated to reduce the dependence of the capacitance between the gate metal electrode and the conductive layer C_gd upon a bias voltage being applied between the gate metal electrode and the conductive layer.

Claims

1. A TFT stack for a liquid crystal display, the stack comprising:

a silicon layer comprising a heavily doped region, a non-doped region, and a lightly doped region between the heavily doped region and the non-doped region, the heavily doped region being hydrogenated;

an insulation layer comprising a first portion formed over the lightly doped region and a second portion disposed over the non-doped region;

a gate metal electrode layer formed over the second portion of the non-doped region;

a first dielectric layer disposed over the gate metal electrode and over the first portion of the insulation layer, the first dielectric layer being formed through a chemical vapor deposition (CVD) process at a first temperature, wherein a via is formed above the heavily doped region; and

a conductive layer over the via to contact the heavily doped region, wherein the heavily doped region is hydrogenated to reduce the dependence of the capacitance between the gate metal electrode and the conductive layer C_gd upon a bias voltage being applied between the gate metal electrode and the conductive layer.

2. The TFT stack of claim 1, wherein the silicon comprises a plurality of crystals, the plurality of crystals being aligned in orientation <

100>

to reduce the dependence of the capacitance C_gd upon the bias voltage.

3. The TFT stack of claim 1, further comprising a second dielectric layer disposed over the first dielectric layer, the second dielectric layer being formed through the CVD process at a second temperature higher than the first temperature.

4. The TFT stack of claim 3, wherein the first and second dielectric layers comprise silicon oxide or silicon nitride.

5. The TFT stack of claim 1, wherein the conductive layer comprises indium-tin oxide.

6. A method for fabricating a TFT stack, the method comprising:

depositing a silicon layer on a substrate, the silicon layer comprising a heavily doped region, a non-doped region, and a lightly doped region between the heavily doped region and the non-doped region;

forming an insulation layer having a first portion over the lightly doped region and a second portion over the non-doped region;

forming a gate metal electrode over the second portion of the insulation layer above the non-doped region of the silicon layer;

depositing a first dielectric layer over the gate metal electrode by using a mixture of precursors comprising hydrogen containing precursors during a chemical vapor deposition (CVD), over the first portion of the insulator layer above the lightly doped region, and over the heavily doped region of the silicon layer at a first temperature;

hydrogenating the heavily doped region of the silicon layer to reduce the dependence of the capacitance between the gate metal and the heavily doped region upon a bias voltage; and

forming a via through the first and second dielectric layers above the heavily doped region; and

depositing a conductive layer over the via.

7. The method of claim 6, further comprising crystallizing a plurality of crystals in the silicon layer to align the plurality of crystals in orientation <

100>

.

8. The method of claim 6, wherein the precursors is selected from a group consisting of silane (SiH₄), ammonia (NH₃), nitrous oxide (N₂O), hydrogen (H₂), and nitrogen (N₂).

9. The method of claim 6, wherein the hydrogen containing precursors is selected from a group consisting of SiH₄, NH₃, and H₂.

10. The method of claim 6, wherein the first temperature is about 300°

C.

11. The method of claim 6, wherein the second temperature ranges from about 320°

C. to 350°

C.

12. The method of claim 6, wherein the second dielectric layer is thicker than the first dielectric layer.

13. The method of claim 6, wherein the first and second dielectric layers comprise silicon oxide or silicon nitride.

14. A TFT for a liquid crystal display (LCD) having an array of pixels, the TFT comprising:

a silicon layer comprising a plurality of crystals, the plurality of crystals being aligned in the orientation <

100>

to reduce the dependence of the capacitance between a gate electrode and the heavily doped drain region of the silicon C_gd upon a bias voltage;

an insulation layer comprising a first portion over the lightly doped region and a second portion over the non-doped region;

the gate electrode over the second portion of the insulation layer above the non-doped region;

a dielectric layer disposed over the gate metal electrode and over the first portion of the insulation layer, such that a via is formed above the heavily doped region; and

a conductive layer over the via to connect to the heavily doped region, the bias voltage being applied between the gate electrode and the conductive layer.

15. The TFT of claim 14, wherein the dielectric layer comprises:

a first dielectric layer disposed over the gate metal electrode, the first dielectric layer being formed through a chemical vapor deposition (CVD) process at a first temperature; and

a second dielectric layer disposed over the first dielectric layer, the second dielectric layer being formed through the CVD process at a second temperature higher than the first temperature.

16. The TFT of claim 15, wherein the CVD comprises a mixture of precursors comprising hydrogen containing precursors.

17. The TFT of claim 15, wherein the first temperature is about 300°

C.

18. The TFT of claim 15, further comprising depositing a second dielectric layer over the first dielectric layer at a second temperature higher than the first temperature, wherein the second temperature ranges from about 320°

C. to 350°

l C.

19. The TFT of claim 18, wherein the second dielectric layer is thicker than the first dielectric layer.

20. The TFT of claim 18, wherein the first and second dielectric layers comprise silicon oxide or silicon nitride.

21. The TFT of claim 15, wherein the conductive layer comprises indium-tin oxide.