Source/Drain Re-Growth for Manufacturing III-V Based Transistors

• US 20140070276A1
• Filed: 11/14/2013
• Published: 03/13/2014
• Est. Priority Date: 06/01/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ko, Chih-Hsin, Wann, Clement Hsingjen
• Granted Patent: US 9,006,788 B2
• Time in Patent Office: Days
• US Class Current: 257/192
• CPC Class Codes: H01L 21/28264 the insulator being formed after the semiconductor body, the semiconductor being a III-V compound
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66863 Lateral single gate transistors
• CPC Class Codes: H01L 29/7783 using III-V semiconductor material
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/8128 with recessed gate

Abstract

A method of forming an integrated circuit structure includes providing a substrate, and epitaxially growing a first semiconductor layer over the substrate. The first semiconductor layer includes a first III-V compound semiconductor material formed of group III and group V elements. The method further includes forming a gate structure on the first semiconductor layer, and forming a gate spacer on at least one sidewall of the gate structure. After the step of forming the gate structure, a second semiconductor layer including a second III-V compound semiconductor material is epitaxially grown on the first semiconductor layer.

Claims

1. An integrated circuit structure comprising:

a substrate;

a first semiconductor layer over the substrate, wherein the first semiconductor layer comprises a first III-V compound semiconductor material formed of group III and group V elements;

a gate structure on the first semiconductor layer;

a gate spacer on at least one sidewall of the gate structure; and

a second semiconductor layer comprising a second III-V compound semiconductor material over the first semiconductor layer, wherein the gate spacer adjoins the second semiconductor layer and the gate structure, and wherein the gate spacer spaces apart the second semiconductor layer from the gate structure.

2. The integrated circuit structure of claim 1, wherein the first semiconductor layer further comprises:

a bottom barrier;

a channel layer over the bottom barrier; and

a top barrier over the channel layer, wherein bandgaps of the bottom barrier and the top barrier are greater than a bandgap of the channel layer.

3. The integrated circuit structure of claim 1, wherein an interface between the first semiconductor layer and the second semiconductor layer is level with an interface between the first semiconductor layer and the gate structure.

4. The integrated circuit structure of claim 1, wherein the second semiconductor layer is doped with an element selected from the group consisting essentially of Si, Zn, Be, and combinations thereof.

5. The integrated circuit structure of claim 1, wherein the second semiconductor layer further comprises:

a first sub-layer comprising the second III-V compound semiconductor material and having a first bandgap; and

a second sub-layer having a second bandgap smaller than the first bandgap, wherein the second sub-layer comprises a third III-V compound semiconductor material doped with an element selected from the group consisting essentially of Si, Zn, Be, and combinations thereof

6. The integrated circuit structure of claim 1, wherein the gate structure comprises a gate dielectric and a gate electrode over the gate dielectric.

7. The integrated circuit structure of claim 1, wherein the gate structure comprises a gate electrode contacting the second semiconductor layer.

8. An integrated circuit structure comprising:

a semiconductor substrate;

a first semiconductor layer over the semiconductor substrate, wherein the first semiconductor layer comprises a first III-V compound semiconductor material formed of group III and group V elements;

a gate structure on the first semiconductor layer;

a gate spacer on at least one sidewall of the gate structure; and

a second semiconductor layer comprising a second III-V compound semiconductor material over the first semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer have an interface level with a bottom surface of the gate structure and a bottom surface of the gate spacer.

9. The integrated circuit structure of claim 8, wherein the first semiconductor layer and the second semiconductor layer have different compositions.

10. The integrated circuit structure of claim 8, wherein the first semiconductor layer and the second semiconductor layer have a same composition and a same bandgap.

11. The integrated circuit structure of claim 8, wherein the first semiconductor layer further comprises:

a bottom barrier;

a channel layer over the bottom barrier; and

a top barrier over the channel layer, wherein bandgaps of the bottom barrier and the top barrier are greater than a bandgap of the channel layer.

12. The integrated circuit structure of claim 11, wherein the second semiconductor layer further comprises:

a first sub-layer formed of the second III-V compound semiconductor material, wherein the first sub-layer has a bandgap greater than a bandgap of the channel layer; and

a second sub-layer formed of a third III-V compound semiconductor material, wherein the second sub-layer has a bandgap smaller than the bandgap of the first sub-layer.

13. The integrated circuit structure of claim 8 further comprising a metal layer over and contacting the second semiconductor layer.

14. An integrated circuit structure comprising:

a substrate;

a first semiconductor layer over the substrate, wherein the first semiconductor layer comprises a first III-V compound semiconductor material formed of group III and group V elements;

a gate structure on the first semiconductor layer;

a gate spacer on at least one sidewall of the gate structure; and

a second semiconductor layer comprising a group IV semiconductor material as a majority element over the first semiconductor layer, wherein the gate spacer adjoins the second semiconductor layer and the gate structure, and wherein the gate spacer spaces apart the second semiconductor layer from the gate structure.

15. The integrated circuit structure of claim 14, wherein the first semiconductor layer further comprises:

a bottom barrier;

a channel layer over the bottom barrier; and

a top barrier over the channel layer, wherein bandgaps of the bottom barrier and the top barrier are greater than a bandgap of the channel layer.

16. The integrated circuit structure of claim 14 further comprising a metal layer overlying and contacting the second semiconductor layer.