METHODS OF FORMING SEMICONDUCTOR DEVICES WITH SELF-ALIGNED CONTACTS AND THE RESULTING DEVICES

• US 20140070285A1
• Filed: 09/12/2012
• Published: 03/13/2014
• Est. Priority Date: 09/12/2012
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.), International Business Machines Corporation
• Original Assignee: GlobalFoundries, Inc., International Business Machines Corporation
• Inventors: Xie, Ruilong, Shom, Ponoth, Cai, Xiuyu, Pranatharthiharan, Balasubramanian, Miller, Robert J.
• Granted Patent: US 8,753,970 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled

Abstract

One method includes forming a sacrificial gate structure above a substrate, forming a first sidewall spacer adjacent a sacrificial gate electrode, removing a portion of the first sidewall spacer to expose a portion of the sidewalls of the sacrificial gate electrode, and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode and above a residual portion of the first sidewall spacer. The method further includes forming a first layer of insulating material above the liner layer, forming a second sidewall spacer above the first layer of insulating material and adjacent the liner layer, performing an etching process to remove the second sidewall spacer and sacrificial gate cap layer to expose an upper surface of the sacrificial gate electrode, removing the sacrificial gate electrode to define a gate cavity at least partially defined laterally by the liner layer, and forming a replacement gate structure in the cavity.

Claims

1. A method, comprising:

forming a sacrificial gate structure and a sacrificial gate cap layer above a semiconducting substrate, said sacrificial gate structure comprising at least a sacrificial gate electrode that has a plurality of sidewalls;

forming at least one first sacrificial sidewall spacer adjacent said sacrificial gate electrode;

performing at least one etching process to remove a portion of said first sacrificial sidewall spacer and thereby expose at least a portion of said sidewalls of said sacrificial gate electrode;

after performing said etching process, forming a liner layer on said exposed sidewalls of said sacrificial gate electrode and above a residual portion of said first sacrificial sidewall spacer;

forming a first layer of insulating material above said liner layer;

forming at least one second sacrificial sidewall spacer above said first layer of insulating material and adjacent said liner layer;

forming a second layer of insulating material adjacent said second sacrificial sidewall spacer;

performing at least one etching process to remove at least said second sacrificial sidewall spacer and said sacrificial gate cap layer to thereby define an opening in said second layer of insulating material that exposes an upper surface of said sacrificial gate electrode;

after exposing said upper surface of said sacrificial gate electrode, removing at least said sacrificial gate electrode to thereby define a gate cavity that is at least partially defined laterally by said liner layer; and

forming a replacement gate structure in said gate cavity.

2. The method of claim 1, wherein said liner layer is comprised of silicon nitride or silicon oxynitride.

3. The method of claim 1, wherein said first and second layers of insulating material are comprised of silicon dioxide.

4. The method of claim 1, wherein said sacrificial gate structure is comprised of a silicon dioxide gate insulation layer and a polysilicon gate electrode positioned above said gate insulation layer.

5. The method of claim 1, wherein said replacement gate structure comprises a gate insulation layer comprised of a high-k insulating material and a gate electrode comprised of at least one layer of metal.

6. The method of claim 1, wherein said step of removing at least said sacrificial gate electrode comprises performing at least one etching process to remove at least said sacrificial gate electrode.

7. The method of claim 1, further comprising forming a non-sacrificial sidewall spacer within said opening in said second layer of insulating material, said non-sacrificial sidewall spacer defining a gate cap cavity within said second layer of insulating material above said replacement gate structure.

8. The method of claim 7, further comprising forming a final gate cap layer in said gate cap cavity above said replacement gate structure.

9. The method of claim 8, further comprising:

after forming said final gate cap layer, forming a third layer of insulating material above said final gate cap layer;

forming a contact opening in said first, second and third layers of insulating material that exposes a source/drain region formed in said substrate proximate said replacement gate structure; and

forming a self-aligned contact in said contact opening that is conductively coupled to said source/drain region.

10. The method of claim 8, further comprising:

performing at least one etching process to remove at least said first and second layers of insulating material, which thereby defines a recess under said non-sacrificial sidewall spacer; and

forming a low-k sidewall spacer that is at least partially positioned within said recess under said non-sacrificial spacer and adjacent said liner layer.

11. The method of claim 10, wherein said step of forming said low-k spacer in said recess and adjacent said liner layer comprises:

depositing a layer of low-k insulating material above said final gate cap, said non-sacrificial sidewall spacers and in said recess on said liner layer; and

performing an anisotropic etching process on said layer of low-k insulating material.

12. The method of claim 1, further comprising forming metal silicide regions on source/drain regions formed in said substrate adjacent said replacement gate structure.

13. The method of claim 12, further comprising;

forming a third layer of insulating material above said substrate and said metal silicide regions;

forming a plurality of contact openings in said first, second and third layers of insulating material that exposes said metal silicide regions; and

forming a self-aligned contact in each of said contact openings that is conductively coupled to one of said metal silicide regions.

14. A device, comprising:

a gate structure positioned above a semiconducting substrate, said gate structure comprising a gate insulation layer and a gate electrode, said gate insulation layer having two upstanding portions that are substantially vertically oriented relative to an upper surface of said substrate;

a gate cap layer positioned above said gate electrode;

a sidewall spacer positioned adjacent said gate cap layer;

a liner layer of silicon nitride or silicon oxynitride positioned on at least a portion of each of said two upstanding portions of said gate insulation layer; and

an insulating material, at least a portion of which is positioned on said liner layer and under said sidewall spacer.

15. The device of claim 14, wherein said insulating material is a low-k sidewall spacer.

16. The device of claim 15, wherein said low-k sidewall spacer is comprised of a material having a k value of less than 6.

17. The device of claim 14, wherein said gate insulation layer is comprised of a high-k insulating material and said gate electrode is comprised of at least one layer of metal.

18. The device of claim 15, further comprising a self-aligned contact that contacts said low-k spacer.

19. The device of claim 14, wherein said sidewall spacer and said gate cap layer are comprised of silicon nitride.

20. The device of claim 14, wherein said insulating material is a layer of insulating material that is positioned above a plurality of source/drain regions formed in said substrate proximate said gate structure.

21. The device of claim 20, further comprising a metal silicide region formed on each of said source/drain regions.

22. The device of claim 21, further comprising a plurality of self-aligned contacts positioned in said layer of insulating material, wherein each of said self-aligned contacts is conductively coupled to one of said metal silicide regions.