Double-Resurf LDMOS With Drift And PSURF Implants Self-Aligned To A Stacked Gate "BUMP" Structure

• US 20140070315A1
• Filed: 11/14/2013
• Published: 03/13/2014
• Est. Priority Date: 10/29/2008
• Status: Active Grant

• Current Assignee: Tower Semiconductor Limited
• Original Assignee: Tower Semiconductor Limited
• Inventors: Levin, Sharon, Levy, Sagy, Berkovitch, Noel
• Granted Patent: US 9,484,454 B2
• Time in Patent Office: Days
• US Class Current: 257/343
• CPC Class Codes: H01L 21/02233 of the semiconductor substrate or a semiconductor layer
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/2253 by ion implantation
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/32 using masks
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/0617 comprising components of the field-effect type H01L27/0251 takes precedence
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 : Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 : Field plates
• CPC Class Codes: H01L 29/42368 : the thickness being non-uniform
• CPC Class Codes: H01L 29/66681 : Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/66689 : with a step of forming an insulating sidewall spacer forming insulating material on a substrate H01L21/02107
• CPC Class Codes: H01L 29/7816 : Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

A double-RESURF LDMOS transistor has a gate dielectric structure including a shallow field “bump” oxide region and an optional raised dielectric structure that provides a raised support for the LDMOS transistor'"'"'s polysilicon gate electrode. Fabrication of the shallow field oxide region is performed through a hard “bump” mask and controlled such that the bump oxide extends a minimal depth into the LDMOS transistor'"'"'s drift (channel) region. The hard “bump” mask is also utilized to produce an N-type drift (N-drift) implant region and a P-type surface effect (P-surf) implant region, whereby these implants are “self-aligned” to the gate dielectric structure. The N-drift implant is maintained at Vdd by connection to the LDMOS transistor'"'"'s drain diffusion. An additional Boron implant is utilized to form a P-type buried layer that connects the P-surf implant to the P-body region of the LDMOS transistor, whereby the P-surf implant is maintained at 0V.

Claims

1. An LDMOS transistor fabricated on a semiconductor substrate, the transistor comprising:

a well region located in the semiconductor substrate and having a first conductivity type;

a base oxide layer located on an upper surface of the semiconductor substrate over a first portion of the well region;

a gate dielectric structure including a shallow field oxide region having a birds beak profile extending below the upper surface of the semiconductor substrate over a second portion of the well region;

a gate electrode including a first portion disposed over the base oxide layer and a second portion disposed over a portion of the gate dielectric structure;

a drift implant formed by a diffused dopant having the first conductivity type and disposed in the well region below the gate dielectric structure; and

a surface field implant formed by a diffused dopant having a second conductivity type and disposed in the well region below the drift implant,

wherein the drift implant and the surface field implant are self-aligned to the gate dielectric structure such that opposing edges of the gate dielectric structure are substantially aligned with corresponding outer boundary edges of the drift implant and the surface implant.

2. The LDMOS transistor of claim 1,

wherein the substrate includes a plurality of shallow trench isolation (STI) regions disposed adjacent to the double-RESURF LDMOS transistor, each said STI region extending at least a first depth below the upper surface of the semiconductor substrate, and

wherein the shallow field oxide region of the stacked gate dielectric structure extends a second depth below the upper surface of the semiconductor substrate, wherein the first depth is greater than the second depth.

3. The LDMOS transistor of claim 2, wherein the first depth is at least ten times larger than the second depth.

4. The LDMOS transistor of claim 2, wherein the second depth is 250 Angstroms or less.

5. The LDMOS transistor of claim 2,

wherein the gate dielectric structure further comprises a raised dielectric structure disposed entirely on the shallow field oxide region, and

wherein edges of both the shallow field oxide region and the raised dielectric structure are substantially aligned with each other and with said corresponding outer boundary edges of the drift implant and the surface implant.

6. The LDMOS transistor of claim 1, further comprising:

a diffusion body region formed by a dopant having the second conductivity type located in the first portion of the well region;

a first buried layer formed by a dopant having the first conductivity type and disposed in a lower portion of the well region; and

a second buried layer formed by a dopant having the second conductivity type disposed in the well region above the first buried layer, wherein the second buried layer extends under the diffusion body region and the surface field implant such that the surface field implant is maintained at a first voltage level of said diffusion body region.

7. The LDMOS transistor of claim 6, further comprising a drain region formed by a diffused dopant having the first conductivity type and disposed in the well region adjacent to the gate dielectric structure, wherein said drift implant is electrically connected to the drain region such that the drift implant is maintained at a second voltage level of said drain region.

8. A double-RESURF LDMOS transistor fabricated on a semiconductor substrate, the transistor comprising:

a well region located in the semiconductor substrate having a first conductivity type;

a base oxide layer located on an upper surface of the semiconductor substrate over a first portion of the well region;

a gate dielectric structure located over a second portion of the well region;

a gate electrode disposed over a portion of the base oxide layer and a portion of the gate dielectric structure;

a drain region formed by a diffused dopant having the first conductivity type and disposed in the well region adjacent to the gate dielectric structure;

a drift implant formed by a diffused dopant having the first conductivity type and disposed in the well region below the gate dielectric structure;

a surface field implant formed by a diffused dopant having a second conductivity type and disposed in the well region below the drift implant such that the drift implant and the surface field implant form a horizontal PN junction;

a diffusion body region formed by a dopant having the second conductivity type located in the first portion of the well region;

a first buried layer formed by a dopant having the first conductivity type and disposed in a lower portion of the well region; and

a second buried layer formed by a dopant having the second conductivity type disposed in the well region above the first buried layer,

wherein the second buried layer extends between the diffusion body region and the surface field implant such that the surface field implant is maintained at a first voltage level of said diffusion body region, and

wherein said drift implant is electrically connected to the drain region such that the drift implant is maintained at a second voltage level of said drain region.

9. The double-RESURF LDMOS transistor of claim 8, further comprising:

a diffusion body region formed by a dopant having the second conductivity type located in the first portion of the well region;

a first buried layer formed by a dopant having the first conductivity type and disposed in a lower portion of the well region; and

a second buried layer formed by a dopant having the second conductivity type disposed in the well region above the first buried layer, wherein the second buried layer extends under the diffusion body region and the surface field implant.

10. A method of fabricating a double-RESURF LDMOS transistor on a semiconductor structure, the method comprising:

forming a well region in the semiconductor substrate using a dopant having a first conductivity type, and a base oxide layer on an upper surface of the semiconductor substrate over a first portion of the well region;

forming a mask on the upper surface such that the mask defines an opening that exposes a portion of the upper surface located over a second portion of the well region;

forming a drift implant region and a surface field implant in the semiconductor substrate by implanting associated dopant materials through the opening defined in the mask;

forming a gate dielectric structure inside the opening defined in the mask such that both the n-type implant and the p-type surface field implant are self-aligned to the gate dielectric structure;

removing the mask; and

forming a gate electrode on a portion of the base oxide layer and a portion of the gate dielectric structure.

11. The method of claim 10, further comprising:

performing a first implant process during which an N-type dopant is implanted in a first region of a base semiconductor portion;

performing a second implant process during which a P-type dopant is implanted in a second region of the base semiconductor substrate, the second region overlapping the first region;

forming an epitaxial layer over the base portion, wherein said semiconductor substrate includes the base semiconductor portion, and the epitaxial silicon layer, and the upper surface of the semiconductor substrate is formed by an exposed surface of the epitaxial layer; and

annealing the semiconductor substrate such that the P-type dopant and the N-type dopant diffuse into the epitaxial layer to form a P-type buried layer and an N-type buried layer, wherein the P-type buried layer is disposed over the N-type buried layer,

wherein forming the well region in the semiconductor substrate comprises forming the well region such that it extends from the upper surface to the N-type buried layer.

12. The method of claim 11, further comprising:

performing a sinker implant process during which an N-type sinker dopant is implanted in a region of the epitaxial layer; and

performing a sinker-drive anneal process in which the dopant diffuses through the epitaxial layer and forms a sinker implant process extending between the upper surface and the N-type buried layer.

13. The method of claim 10, wherein forming the mask comprises:

depositing a nitride hard mask layer over the upper surface of the semiconductor substrate;

depositing a photoresist layer on the nitride hard mask layer; and

patterning the nitride hard mask layer and the photoresist layer to define the opening.

14. The method of claim 13, wherein forming the drift implant region and the surface field implant comprises:

performing a high energy implant process through the opening during which a p-type dopant material is implanted in the semiconductor substrate and forms said surface field implant at a first distance below the upper surface of the substrate; and

performing a low energy implant process through the opening during which an n-type implant material is implanted in the semiconductor substrate and forms said drift implant region at a second distance D2 below the upper surface of the substrate, the second distance between located between the first distance and the upper surface of the semiconductor substrate.

15. The method of claim 14, wherein forming the gate dielectric structure comprises forming a shallow field oxide region by thermally oxidizing the exposed portion of the drain diffusion region through the opening of the mask.

16. The method of claim 15, further comprising:

forming a plurality of shallow trench isolation (STI) regions in the epitaxial layer such that each said STI region extends at least a first depth below the upper surface of the semiconductor substrate,

wherein forming the gate dielectric structure comprises forming the shallow field oxide region such that it extends a second depth below the upper surface of the semiconductor substrate, wherein the first depth is greater than the second depth.

17. The method of claim 16, wherein forming the gate dielectric structure further comprises forming a dielectric structure on the shallow field oxide region such that edges of the dielectric structure are defined by inside walls of the opening defined in the mask, whereby the dielectric structure is entirely disposed over the shallow field oxide region.

18. The method of claim 17, wherein forming the dielectric structure on the shallow field oxide region comprises:

depositing a dielectric layer over the mask such a portion of the dielectric layer extends into the opening defined in the mask and contacts the thermal oxide region; and

removing portions of the dielectric layer that do not extend into the opening of the mask, wherein a remaining portion of the dielectric layer forms the dielectric structure.

19. The method of claim 18, wherein the step of removing portions of the dielectric layer that do not extend into the opening of the mask comprises performing chemical-mechanical polishing (CMP).

20. The method of claim 15, further comprising forming drain implants by directing an associated dopant material at a tilt angle in the range of 45 to 60°

into the substrate such that the drain implants are formed up to a birds beak region of said shallow field oxide region.

21. The method of claim 15, further comprising forming drain implants by directing an associated dopant material through a portion of the nitride hard mask layer.