SEMICONDUCTOR DEVICE

• US 20140070368A1
• Filed: 02/12/2013
• Published: 03/13/2014
• Est. Priority Date: 05/14/2012
• Status: Active Grant

• Current Assignee: Noda Screen Co., Ltd.
• Original Assignee: Noda Screen Co., Ltd.
• Inventors: Oyamada, Seisei, Yoshizawa, Masamitsu, Ogawa, Hirotaka
• Granted Patent: US 9,153,549 B2
• Time in Patent Office: Days
• US Class Current: 257/532
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/14133 with a staggered arrangement, e.g. depopulated array
• CPC Class Codes: H01L 2224/14135 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 2225/0652 Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/15 Ceramic or glass substrates H01L23/142, H01L23/145, H01L23/147 take precedence
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 23/64 Impedance arrangements
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/07 Structure, shape, material or disposition of the bonding areas after the connecting process
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/15321 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/171 : Frame
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H05K 1/141 : One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence
• CPC Class Codes: H05K 2201/10378 : Interposers
• CPC Class Codes: H05K 2201/10515 : Stacked components
• CPC Class Codes: H05K 2201/2036 : Permanent spacer or stand-off in a printed circuit or printed circuit assembly
• CPC Class Codes: H05K 3/368 : parallel to each other H05K3/361 takes precedence

Abstract

A semiconductor device includes a semiconductor chip, an interposer, a surface circuit pattern, and a post array. The surface circuit pattern is formed on one surface of the interposer and includes chip side pads connected to an external connection pad of the semiconductor chip, junction pads, and interconnecting lines having an end connected to the chip side pads and another end connected to the junction pads. The interconnecting lines extend from the chip side pads toward an outer edge of the interposer. The post array includes conducting paths and insulating resin insulating the conductive paths from each other. The post array is arranged such that the conductive paths extend in a direction intersecting with the surface of the interposer. The conducting paths each have an end connected to the junction pad and another end to be connected to the printed wiring board.

Claims

1. A semiconductor device to be mounted on a printed wiring board, the semiconductor device comprising:

a semiconductor chip including a predetermined semiconductor integrated circuit and an external connection pad configured to connect the semiconductor integrated circuit to an external circuit;

an interposer made of silicon or glass;

a surface circuit pattern formed on one surface of the interposer, the surface circuit pattern including;

chip side pads provided on the surface of the interposer and connected to the external connection pad of the semiconductor chip;

junction pads; and

interconnecting lines having an end connected to the chip side pads and another end connected to the junction pads, the interconnecting lines extending from the chip side pads toward an outer edge of the interposer; and

a post array including a plurality of conducting paths and insulating resin insulating the conductive paths from each other, the post array being arranged such that the conductive paths extend in a direction intersecting with the surface of the interposer, the conducting paths each having an end connected to the junction pad and another end to be connected to the printed wiring board.

2. The semiconductor device according to claim 1, further comprising a by-pass capacitor for a power supply system of the semiconductor chip or a clamp diode for I/O terminal on the surface of the interposer on which the surface circuit pattern is formed.

3. The semiconductor device according to claim 2, wherein the external connection pad for an I/O power source is connected to a surface electrode by soldering, the surface electrode being formed on the surface of the interposer and included in the by-pass capacitor.

4. The semiconductor device according to claim 1, wherein the post array is produced by cutting a base member including a plurality of metal wires and insulating resin in a direction intersecting with the metal wires, the metal wires being arranged such that axes thereof are parallel to each other and separated from each other by the insulating resin.

5. The semiconductor device according to claim 1, wherein the post array includes a plurality of post arrays, and

the post arrays are spaced apart from each other and connected to the semiconductor chip.