Chip To Package Interface

• US 20140070420A1
• Filed: 09/12/2012
• Published: 03/13/2014
• Est. Priority Date: 09/12/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Sapone, Giuseppina
• Granted Patent: US 8,890,319 B2
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: H01F 19/04 Transformers or mutual inductances suitable for handling frequencies considerably beyond the audio range resonant circuits H03H
• CPC Class Codes: H01F 27/2804 Printed windings
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

In accordance with an embodiment of the present invention, a semiconductor package includes a semiconductor chip disposed within an encapsulant, and a first coil disposed in the semiconductor chip. A dielectric layer is disposed above the encapsulant and the semiconductor chip. A second coil is disposed above the dielectric layer. The first coil is magnetically coupled to the second coil.

Claims

1. A semiconductor package comprising:

a semiconductor chip disposed within an encapsulant;

a first coil disposed in the semiconductor chip;

a dielectric layer disposed above the encapsulant and the semiconductor chip; and

a second coil disposed above the dielectric layer, the first coil being magnetically coupled to the second coil.

2. The semiconductor package of claim 1, further comprising:

a plurality of contact pads in the semiconductor chip;

a plurality of external contact pads disposed above the encapsulant; and

a redistribution line coupling a pad of the plurality of contact pads with a pad of the plurality of external contact pads, the redistribution line and the second coil disposed in a same redistribution layer.

3. The semiconductor package of claim 1, further comprising a second dielectric layer disposed within the semiconductor chip, the second dielectric layer disposed between the dielectric layer and the first coil.

4. The semiconductor package of claim 1, further comprising a metal line disposed below and electrically coupled to the first coil in the semiconductor chip, the metal line being magnetically coupled to the second coil.

5. The semiconductor package of claim 1, further comprising a metal loop disposed within the first coil and the semiconductor chip, wherein the metal loop has a smaller diameter than the first coil and is electrically coupled to the first coil.

6. The semiconductor package of claim 1, further comprising a metal loop disposed within the second coil and the dielectric layer, wherein the metal loop has a smaller diameter than the second coil and is electrically coupled to the second coil.

7. The semiconductor package of claim 1, wherein the second coil has a first end and a second end, the first end being coupled to a ground potential node.

8. The semiconductor package of claim 7, wherein the second end is coupled to a node coupled to receiver/transmitter input/output node of an antenna.

9. The semiconductor package of claim 1, wherein the second coil has a first end and a second end, the first end being coupled to a first differential input/output node and the second end being coupled to a second differential input/output node.

10. The semiconductor package of claim 1, wherein the semiconductor chip comprises differential signal input/output interface, and wherein the semiconductor package comprises single-ended signal input/output interface.

11. A semiconductor device comprising:

a first coil of a transformer disposed within a semiconductor chip; and

a second coil of the transformer disposed within an insulating material outside the semiconductor chip, the first and the second coils forming the transformer.

12. The semiconductor device of claim 11, wherein the second coil is coupled to a receiver/transmitter node of the semiconductor device.

13. The semiconductor device of claim 11, wherein the second coil is coupled to a differential pair signal circuit.

14. The semiconductor device of claim 11, wherein the transformer is configured to implement a differential to single ended conversion.

15. The semiconductor device of claim 11, wherein the transformer is configured to implement a differential to differential operation.

16. The semiconductor device of claim 11, wherein the first coil is disposed in more than one metal level within the semiconductor chip.

17. The semiconductor device of claim 11, wherein the second coil is disposed in more than one level of a redistribution layer of the semiconductor device.

18. The semiconductor device of claim 11, wherein the first coil is a multi-turn coil.

19. The semiconductor device of claim 11, wherein the second coil is a multi-turn coil.

20. A method of forming a semiconductor package, the method comprising:

forming a semiconductor chip having a first coil disposed in an uppermost metal level;

forming a reconstituted wafer comprising the semiconductor chip;

forming a dielectric layer over the reconstituted wafer; and

forming a second coil over the dielectric layer, the second coil being configured to magnetically couple with the first coil.

21. The method of claim 20, further comprising:

coupling a first differential output of a differential signal from the semiconductor chip to a first end of the first coil; and

coupling a second differential output of the differential signal to a second end of the first coil.

22. The method of claim 20, further comprising coupling one end of the second coil to a ground potential node.

23. The method of claim 20, further comprising singulating the reconstituted wafer after forming the second coil.

24. The method of claim 20, wherein forming the semiconductor chip having the first coil disposed in the uppermost metal level comprises forming the first coil within the upper metal level and a metal level lower than the upper metal level.

25. The method of claim 20, further comprising forming redistribution lines in the dielectric layer.

26. The method of claim 20, further comprising coupling each end of the second coil to an external contact pad.