Determination and Reduction of Parasitic Capacitance Variation Due to Display Noise

• US 20140071087A1
• Filed: 09/10/2013
• Published: 03/13/2014
• Est. Priority Date: 09/10/2012
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Yousefpor, Marduke, Poon, Stephen S.
• Granted Patent: US 9,329,738 B2
• Time in Patent Office: Days
• US Class Current: 345/174
• CPC Class Codes: G06F 3/04184 Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally
• CPC Class Codes: G06F 3/044 by capacitive means

Abstract

Embodiments described herein generally take the form of methods and systems for identifying and/or reducing a parasitic capacitance variation in a capacitive integrated touch-sensing module that may arise from proximity to a nearby electronic display.

Claims

1. A method for reducing a parasitic capacitance between a display and a capacitive-touch sensing panel;

comprising;

generating an admittance model of a plurality of parasitic capacitances between plurality of pixels;

varying one or more of the plurality of parasitic capacitances in the admittance model;

determining if the variance of the one or more of plurality of parasitic capacitances reduces an overall parasitic capacitance between the display and the capacitive-touch sensing panel; and

if so, implementing the variance in at least one of the capacitive-touch sensing panel and the display.

2. The method of claim 1, wherein the overall parasitic capacitance is an expression of a display to touch-sensing module cross-capacitance.

3. The method of claim 2, further comprising representing one or more of the plurality of parasitic capacitances as one or more phasors.

4. The method of claim 3, wherein the operation of representing one or more of the plurality of parasitic capacitances as one or more phasors comprises:

representing the capacitance of a touch region as a first phasor; and

representing the parasitic capacitance of a nearby display pixel as a second phasor.

5. The method of claim 4, further comprising:

comparing the magnitude of the first phasor to the second phasor, thereby determining the impact of the first phasor on the second phasor.

6. The method of claim 4, further comprising:

mapping a structural change in at least one of the display and the capacitive touch-sensing panel to a change in at least one phasor, thereby determining an effect of the structural change on the overall parasitic capacitance.