RECEIVER, APPARATUS, AND METHODS FOR WIRELESSLY RECEIVING DATA FROM A POWER INFRASTRUCTURE

• US 20140072060A1
• Filed: 09/11/2013
• Published: 03/13/2014
• Est. Priority Date: 09/11/2012
• Status: Active Grant

• Current Assignee: University of Washington
• Original Assignee: University of Washington
• Inventors: Patel, Shwetak N., Cohn, Gabriel A., Reynolds, Matthew S.
• Granted Patent: US 9,064,396 B2
• Time in Patent Office: Days
• US Class Current: 375/257
• CPC Class Codes: G08B 25/06 using power transmission lines
• CPC Class Codes: G08B 29/02 Monitoring continuously signalling or alarm systems
• CPC Class Codes: H04B 2203/5408 using protocols
• CPC Class Codes: H04B 2203/5441 Wireless systems or telephone
• CPC Class Codes: H04B 2203/5445 Local network
• CPC Class Codes: H04B 3/542 the information being in digital form
• CPC Class Codes: H04L 27/14 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04W 24/08 Testing, supervising or monitoring using real traffic

Abstract

Apparatuses, receivers, systems and methods for receiving data via a power line infrastructure. An exemplary apparatus includes a base station configured to receive a signal from a power line of a structure by coupling to the power line through an electrical outlet. The base station may include an impedance matching circuit configured to match an impedance of the power line of the structure, and a receiver coupled to the impedance matching circuit. The receiver may be configured to demodulate the signal received from the power line of the structure, convert the demodulated signal into a digital signal, and provide the digital signal to a decoder.

Claims

1. An apparatus, comprising:

a base station configured to receive a signal from a power line of a structure by coupling to the power line through an electrical outlet, the base station including;

an impedance matching circuit configured to match an impedance of the power line of the structure; and

a receiver coupled to the impedance matching circuit and configured to demodulate the signal received from the power line of the structure, convert the demodulated signal into a digital signal, and provide the digital signal to a decoder.

2. The apparatus of claim 1, further comprising a computer that includes the decoder configured to decode the digital signal, the computer configured to provide data based on the decoded signal.

3. The apparatus of claim 2, wherein the computer is configured to provide an alert based on the decoded signal.

4. The apparatus of claim 3, wherein the computer is configured to provide the alert to a mobile device.

5. The apparatus of claim 1, wherein the computer is configured to provide the data to a user interface of the computer.

6. The apparatus of claim 1, wherein the computer is configured to provide the decoded signal to a secondary computing system, wherein the secondary computing system is configured to provide an alert based on the decoded signal.

7. The apparatus of claim 2, wherein the received signal is encoded using a run-length limited encoding scheme, wherein the decoder is a run-length limiting decoder.

8. The apparatus of claim 2, wherein the received signal is encoded using a combined run-length limited and error correcting code encoding scheme, and wherein the decoder is a run-length limiting decoder.

9. The apparatus of claim 2, wherein the received signal is encoded using an error correcting code encoding scheme.

10. The apparatus of claim 1, wherein the impedance matching circuit is coupled to the electrical outlet, wherein the outlet is coupled to the power line.

11. The apparatus of claim 10, wherein the impedance matching circuit comprises a first circuit forming a loop between two nodes of the electrical outlet, wherein the first circuit comprises a first capacitor coupled between a first node of the two nodes of the electrical outlet an a first node of a primary side of a transformer, wherein the first circuit further comprises a second capacitor coupled between a second node of the two nodes of the electrical outlet and a second node of the primary side of the transformer.

12. The apparatus of claim 11, wherein the impedance matching circuit further comprises a second circuit, the second circuit comprising a secondary side of the transformer magnetically coupled to the primary side of the transformer, wherein secondary side of the transformer is coupled between an output node and a reference node, wherein the second circuit further comprises a resistive element coupled in parallel with the secondary side of the transformer between the output node and the reference node.

13. The apparatus of claim 11, wherein the impedance matching circuit further comprises a second circuit, the second circuit comprising an secondary side of the transformer magnetically coupled to the primary side of the transformer of the first circuit, wherein the secondary side of the transformer is coupled between a first node of a first resistive element and a reference node, wherein the second circuit further comprises a second resistive element coupled in parallel with the secondary side of the transformer between the first node of the first resistive element and the reference node, wherein a second node of the first resistive element is coupled to an output node.

14. The apparatus of claim 11, wherein the first capacitor is coupled to a line node of the electrical outlet, and wherein the second capacitor is coupled to a neutral node of the electrical outlet.

15. The apparatus of claim 1, wherein the base station further comprises:

a low noise amplifier coupled to the impedance match circuit, the low noise amplifier configured to provide a gain to the signal received from the impedance match circuit;

a band select filter configured to filter a carrier frequency from the amplified signal received from the low noise amplifier to provide a first filtered signal;

a mixer configured to combine the first filtered signal with a local oscillator frequency to provide a second filtered signal having an intermediate frequency that is different than the carrier frequency;

a channel select filter configured to filter the second filtered signal based on the intermediate frequency;

a limiting intermediate frequency amplifier configured to provide a gain to the signal path to provide a third filtered signal and to provide a received signal strength indicator (RSSI) signal;

a demodulator configured to provide the demodulated signal; and

at least one analog to digital converter configured to convert the third filtered signal to the digital signal and to convert the RSSI signal to a digital RSSI signal.

16. The apparatus of claim 1, wherein the signal is a long-range, near-field transmission.

17. The apparatus of claim 1, wherein the signal is modulated using a binary frequency shift keying modulation scheme.

18. A non-transitory computer readable medium comprising instructions that, when executed by one or more processing units, cause the one or more processing units to:

detect a transition of a first signal to a first value at a first time;

detect a start of header pulse sequence of a second signal at a second time, wherein a time between the first time and the second time is a predetermined length of time;

receive a data pulse sequence of the second signal after the header pulse sequence; and

responsive to determining that the header pulse sequence is a valid pulse sequence, decode the data pulse sequence based on an encoding scheme.

19. The non-transitory computer readable medium of claim 18, further comprising instructions that, when executed by one or more processing units, cause the one or more processing units to determine a single bit pulse length based on the header pulse sequence.

20. The non-transitory computer readable medium of claim 19, further comprising instructions that, when executed by one or more processing units, cause the one or more processing units to decode the data pulse sequence based on a bit sequence using a state machine.

21. The non-transitory computer readable medium of claim 18, further comprising instructions that, when executed by one or more processing units, cause the one or more processing units to decode the data pulse sequence based on a sequence of pulse widths using a state machine.

22. The non-transitory computer readable medium of claim 18, further comprising instructions that, when executed by one or more processing units, cause the one or more processing units to convert the data pulse sequence to a list of pulses widths.

23. The non-transitory computer readable medium of claim 18, further comprising instructions that, when executed by one or more processing units, cause the one or more processing units to decode the data pulse sequence based on a run-length limited encoding scheme.

24. A method, comprising:

impedance matching a base station to an impedance of a power line of a building;

extracting a signal from the power line, wherein the signal is received at the power line wirelessly from a transmitting device;

demodulating the extracted signals to provide a demodulated signal;

converting the demodulated signal to a digital signal; and

providing the digital signal to a decoder.

25. The method of claim 24, wherein impedance matching the base station to the impedance of the power line comprises attenuating an alternating current power frequency.

26. The method of claim 24, wherein extracting the signal from the power line comprises converting the signal having a carrier frequency received at the base station to an intermediate signal having an intermediate frequency.

27. The method of claim 26, wherein extracting the signal from the power line comprises filtering the intermediate signal based on the intermediate frequency.

28. The method of claim 26, further comprising providing a received signal strength indicator of the extracted signal to the decoder.

29. The method of claim 26, further comprising amplifying the extracted signal prior to demodulating the extracted signal.