METHODS OF A SERVER WITH A TWO-DIMENSIONAL MAIN MEMORY

• US 20140074880A1
• Filed: 09/03/2013
• Published: 03/13/2014
• Est. Priority Date: 02/12/2008
• Status: Abandoned Application

• Current Assignee: Virident Systems, LLC (Western Digital Corporation)
• Original Assignee: Virident Systems, LLC (Western Digital Corporation)
• Inventors: Karamcheti, Vijay, Ganapathy, Kumar
• Application Number:
  US14/016,223
• Publication Number:
  US 20140074880A1
• Time in Patent Office: Days
• US Class Current: 707/769
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 16/2455 Query execution
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 7/78 for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In one embodiment of the invention, a memory module is disclosed including a printed circuit board with an edge connector; an address controller coupled to the printed circuit board; and a plurality of memory slices. Each of the plurality of memory slices of the memory module includes one or more memory integrated circuits coupled to the printed circuit board, and a slave memory controller coupled to the printed circuit board and the one or more memory integrated circuits. The slave memory controller receives memory access requests for the memory module from the address controller. The slave memory controller selectively activates one or more of the one or more memory integrated circuits in the respective memory slice in response to the address received from the address controller to read data from or write data into selected memory locations in the memory integrated circuits.

Claims

1-56. -56. (canceled)

57. A method in a server comprising:

storing a database in a two dimensional memory array including a plurality of intelligent two dimensional memory modules each having a plurality of processors respectively coupled to memory in a plurality of memory slices;

requesting a search for data be made within the database stored in the memory of the two dimensional memory array;

each of the plurality of processors executing one or more instructions to search for the data within the memory of the memory slice to which they are coupled; and

each of the plurality of processor reporting search results for the data within the memory of the memory slice to which they are coupled.

58. The method of claim 57, wherein

the requesting of the search includes

broadcasting the one or more instructions to each of the plurality of processors.

59. The method of claim 57, further comprising:

aggregating together the search results reported by each of the plurality of processors to form an overall search result for the database stored in the two dimensional memory array.

60-66. -66. (canceled)