Processing Device With Nonvolatile Logic Array Backup

• US 20140075088A1
• Filed: 02/19/2013
• Published: 03/13/2014
• Est. Priority Date: 09/10/2012
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Bartling, Steven Craig, Khanna, Sudhanshu
• Granted Patent: US 10,102,889 B2
• Time in Patent Office: Days
• US Class Current: 711/102
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 11/1032 Simple parity
• CPC Class Codes: G06F 11/1438 Restarting or rejuvenating
• CPC Class Codes: G06F 11/1469 Backup restoration techniques
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57
• CPC Class Codes: G06F 9/4406 Loading of operating system
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: H03K 3/3562 of the master-slave type
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A processing device is operated using a plurality of volatile storage elements. N groups of M volatile storage elements of the plurality of volatile storage elements per group are connected to an N by M size non-volatile logic element array of a plurality of non-volatile logic element arrays using a multiplexer. The multiplexer connects one of the N groups to the N by M size non-volatile logic element array to store data from the M volatile storage elements into a row of the N by M size non-volatile logic element array at one time or to write data to the M volatile storage elements from a row of the N by M size non-volatile logic element array at one time. A corresponding non-volatile logic controller controls the multiplexer operation with respect to the connections between volatile storage elements and non-volatile storage elements.

Claims

1. A computing device apparatus providing non-volatile logic based computing, the apparatus comprising:

a plurality of non-volatile logic element arrays;

a plurality of volatile storage element arrays;

at least one non-volatile logic controller configured to control the plurality of non-volatile logic element arrays to store a machine state represented by corresponding ones of the plurality of volatile storage element arrays and to read out a stored machine state from the plurality of non-volatile logic element arrays to the corresponding ones of the plurality of volatile storage elements;

a multiplexer connected to variably connect individual ones of the volatile storage element arrays to one or more corresponding individual ones of the non-volatile logic element arrays.

2. The computing device apparatus of claim 1 arranged on a single chip.

3. The computing device apparatus of claim 1 wherein the at least one non-volatile logic controller is configured to generate a control sequence for saving the machine state to or retrieving the machine state from the plurality of non-volatile logic element arrays.

4. The computing device apparatus of claim 1 wherein the individual ones of the non-volatile logic element arrays are arranged physically closely to and connected to receive data from corresponding individual ones of the volatile storage elements.

5. The computing device apparatus of claim 1 wherein individual ones of the plurality of volatile storage elements comprise:

a data input port configured to insert data from one of the non-volatile logic element arrays to an associated volatile storage element by allowing passage of a stored data related signal from the one of the non-volatile logic element arrays to a slave stage of the associated volatile storage element in response to receiving an update signal from the at least one non-volatile logic controller on a data input enable port to trigger the data input port.

6. The computing device apparatus of claim 1 wherein the multiplexer is configured to pass states from a plurality of the individual ones of the plurality of volatile storage elements for essentially simultaneous storage in a row of an individual one of the plurality of non-volatile logic element arrays.

7. The computing device apparatus of claim 6 wherein the multiplexer is configured to connect to N groups of M volatile storage elements of the plurality of volatile storage elements per cloud and to an N by M size non-volatile logic element array of the plurality of non-volatile logic element arrays, wherein the multiplexer is configured to connect one of the N groups to the N by M size non-volatile logic element array to store data from the M volatile storage elements into a row of the N by M size non-volatile logic element array at one time.

8. The computing device apparatus of claim 1 wherein the computing device is configured to operate in a retention mode, and the non-volatile logic controller is configured to control and effect storage of data from individual ones of the volatile storage elements into corresponding individual ones of the non-volatile storage elements.

9. The computing device apparatus of claim 1 wherein the computing device is configured to operate in a restore mode in which a clock of the computing device is held in an inactive state for the volatile storage elements, and the non-volatile logic controller is configured to control and effect transfer of data from individual ones of the non-volatile storage elements into corresponding individual ones of the volatile storage elements.

10. The computing device apparatus of claim 1 wherein the at least one non-volatile logic controller is configured to operate independently from a central processing unit for the computing device apparatus.

11. The computing device apparatus of claim 1 wherein individual ones of the plurality of volatile storage elements comprise one of a group consisting of:

flip flop circuit elements, latches, integrated clock gating cells, and combinations thereof.

12. The computing device apparatus of claim 1 wherein individual ones of the plurality of non-volatile logic element arrays comprise ferroelectric capacitor bit cells, flash memory, magnetoresistive random access memory, spin torque magnetoresistive random access memory, and combinations thereof.

13. A method comprising:

operating a processing device using a plurality of volatile storage elements;

connecting N groups of M volatile storage elements of the plurality of volatile storage elements per group and to an N by M size non-volatile logic element array of the plurality of non-volatile logic element arrays using a multiplexer, wherein the multiplexer connects one of the N groups to the N by M size non-volatile logic element array to store data from the M volatile storage elements into a row of the N by M size non-volatile logic element array at one time or to write data to the M volatile storage elements from a row of the N by M size non-volatile logic element array at one time;

controlling the multiplexer using a corresponding non-volatile logic controller.

14. The method of claim 13 further comprising:

determining a backup condition suitable for backing up data stored in the plurality of volatile storage elements;

in response to determining the backup condition;

rendering a clock for the processing device as inactive for the volatile storage elements;

controlling, by the corresponding non-volatile logic controller, storage of a state represented by individual ones of the plurality of volatile storage elements in corresponding ones of a plurality of non-volatile logic element arrays;

determining a recovery condition suitable for recovering data from the plurality of non-volatile logic element arrays to the volatile storage elements;

in response to determining the recovery condition;

holding the clock for the processing device in an inactive state while recovering the state;

controlling, by the corresponding non-volatile logic controller, recovery of the state from the plurality of non-volatile logic element arrays into corresponding ones of the plurality of volatile storage elements.

15. The method of claim 14 wherein the controlling recovery of the state from the plurality of non-volatile logic element arrays into the plurality of volatile storage elements comprises:

the corresponding non-volatile logic controller effecting an update signal at a data input enable port electrically connected to a given volatile storage element to effect inserting data from one of the non-volatile logic element arrays to the given volatile storage element.

16. A computing device apparatus providing non-volatile logic based computing, the apparatus comprising:

at least one non-volatile logic controller separate from a central processing unit for the computing device apparatus;

a plurality of non-volatile logic element arrays comprising ferroelectric capacitor bit cells;

a plurality of volatile storage elements, wherein individual ones of the plurality of volatile storage elements comprise;

flip flop circuit elements;

a data input port configured to insert data from one of the non-volatile logic element arrays to an associated volatile storage element by allowing passage of a stored data related signal from the one of the non-volatile logic element arrays to a slave stage of the associated volatile storage element in response to receiving an update signal from the at least one non-volatile logic controller on a data input enable port to trigger the data input port;

a multiplexer connected to variably connect individual ones of the non-volatile logic element arrays to one or more corresponding individual ones of the volatile storage elements by connecting to N groups of M volatile storage elements of the plurality of volatile storage elements per cloud and to an N by M size non-volatile logic element array of the plurality of non-volatile logic element arrays, wherein the multiplexer is configured to connect one of the N groups to the N by M size non-volatile logic element array to store data from the M volatile storage elements into a row of the N by M size non-volatile logic element array at one time or to write data to the M volatile storage elements from a row of the N by M size non-volatile logic element array at one time;

wherein the at least one non-volatile logic controller is configured to control the plurality of non-volatile logic element arrays to store a machine state represented by the plurality of volatile storage elements and to read out a stored machine state from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements;

wherein the computing device is configured to operate in a backup mode in which the non-volatile logic controller is configured to control and effect storage of data from individual ones of the volatile storage elements into individual ones of the non-volatile storage elements;

wherein the computing device is configured to operate in a restore mode in which a clock of the computing device is held in an inactive state for the volatile storage elements, and the non-volatile logic controller is configured to control and effect transfer of data from individual ones of the non-volatile storage elements into individual ones of the volatile storage elements.

17. The computing device apparatus of claim 16 wherein the individual ones of the non-volatile logic element arrays are arranged physically closely to and connected to receive data from corresponding individual ones of the volatile storage elements.