Nonvolatile Logic Array With Retention Flip Flops To Reduce Switching Power During Wakeup
First Claim
1. A computing device apparatus providing non-volatile logic based computing, the apparatus comprising:
- a plurality of non-volatile logic element arrays;
a plurality of volatile storage elements comprising retention flip flop circuits;
at least one non-volatile logic controller configured to control the plurality of non-volatile logic element arrays to store a machine state represented by the plurality of volatile storage elements and to read out a stored machine state from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements;
wherein individual flip flop circuits comprise a primary logic circuit portion powered by a first power domain and a slave stage circuit portion powered by a second power domain;
wherein the first power domain is configured to be powered down and the second power domain is active during write back of data from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements.
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Accused Products
Abstract
A processing device is operated using a plurality of volatile storage elements. Data in the plurality of volatile storage elements is stored in a plurality of non-volatile logic element arrays. A primary logic circuit portion of individual ones of the plurality of volatile storage elements is powered by a first power domain, and a slave stage circuit portion of individual ones of the plurality of volatile storage elements is powered by a second power domain. During a write back of data from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements, the first power domain is powered down and the second power domain is maintained. In a further approach, the plurality of non-volatile logic element arrays is powered by a third power domain, which is powered down during regular operation of the processing device.
13 Citations
19 Claims
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1. A computing device apparatus providing non-volatile logic based computing, the apparatus comprising:
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a plurality of non-volatile logic element arrays; a plurality of volatile storage elements comprising retention flip flop circuits; at least one non-volatile logic controller configured to control the plurality of non-volatile logic element arrays to store a machine state represented by the plurality of volatile storage elements and to read out a stored machine state from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements; wherein individual flip flop circuits comprise a primary logic circuit portion powered by a first power domain and a slave stage circuit portion powered by a second power domain; wherein the first power domain is configured to be powered down and the second power domain is active during write back of data from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method comprising:
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operating a processing device using a plurality of volatile storage elements; storing data stored in the plurality of volatile storage elements in a plurality of non-volatile logic element arrays; powering a primary logic circuit portion of individual ones of the plurality of volatile storage elements by a first power domain; powering a slave stage circuit portion of individual ones of the plurality of volatile storage elements by a second power domain; powering down the first power domain and maintaining power in the second power domain during a write back of data from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements. - View Dependent Claims (14, 15, 16, 17, 18)
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19. A computing device apparatus providing non-volatile logic based computing, the apparatus comprising:
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at least one non-volatile logic controller separate from a central processing unit for the computing device apparatus; a plurality of non-volatile logic element arrays comprising ferroelectric capacitor bit cells powered by a third power domain; a plurality of volatile storage elements comprising retention flip flop circuit, wherein individual ones of the plurality of the flip flop circuits comprise; a primary logic circuit portion powered by a first power domain, a slave stage circuit portion powered by a second power domain, and a data input port configured to insert data from one of the non-volatile logic element arrays to an associated volatile storage element by allowing passage of a stored data related signal from the one of the non-volatile logic element arrays to a slave stage of the associated volatile storage element in response to receiving an update signal from the at least one non-volatile logic controller on a data input enable port to trigger the data input port; wherein the at least one non-volatile logic controller is configured to control the plurality of non-volatile logic element arrays to store a machine state represented by the plurality of volatile storage elements and to read out a stored machine state from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements; wherein the first power domain is configured to be powered down and the second power domain is active during write back of data from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements; wherein the third power domain is configured to be powered down during regular operation of the computing device apparatus.
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Specification