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Nonvolatile Logic Array With Retention Flip Flops To Reduce Switching Power During Wakeup

  • US 20140075089A1
  • Filed: 02/19/2013
  • Published: 03/13/2014
  • Est. Priority Date: 09/10/2012
  • Status: Active Grant
First Claim
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1. A computing device apparatus providing non-volatile logic based computing, the apparatus comprising:

  • a plurality of non-volatile logic element arrays;

    a plurality of volatile storage elements comprising retention flip flop circuits;

    at least one non-volatile logic controller configured to control the plurality of non-volatile logic element arrays to store a machine state represented by the plurality of volatile storage elements and to read out a stored machine state from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements;

    wherein individual flip flop circuits comprise a primary logic circuit portion powered by a first power domain and a slave stage circuit portion powered by a second power domain;

    wherein the first power domain is configured to be powered down and the second power domain is active during write back of data from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements.

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