Nonvolatile Logic Array Based Computing Over Inconsistent Power Supply

• US 20140075232A1
• Filed: 02/19/2013
• Published: 03/13/2014
• Est. Priority Date: 09/10/2012
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Bartling, Steven Craig, Khanna, Sudhanshu
• Granted Patent: US 9,715,911 B2
• Time in Patent Office: Days
• US Class Current: 713/324
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 11/1032 Simple parity
• CPC Class Codes: G06F 11/1438 Restarting or rejuvenating
• CPC Class Codes: G06F 11/1469 Backup restoration techniques
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57
• CPC Class Codes: G06F 9/4406 Loading of operating system
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: H03K 3/3562 of the master-slave type
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

Input power quality for a processing device is sensed. In response to detection of poor power quality, input power is disconnected, and the processing device backs up its machine state in non-volatile logic element arrays using available stored charge. When power is restored, the stored machine state is restored from the non-volatile logic element arrays to the volatile logic elements whereby the processing device resumes its process from the state immediately prior to power loss allowing seamless processing across intermittent power supply.

Claims

1. A computing device apparatus providing non-volatile logic based computing, the apparatus comprising:

a processing device comprising;

a plurality of non-volatile logic element arrays,

a plurality of volatile storage elements, and

at least one non-volatile logic controller configured to control the plurality of non-volatile logic element arrays to store a machine state represented by the plurality of volatile storage elements and to read out a stored machine state from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements;

a voltage or current detector configured to sense a power quality from an input power supply;

a power management controller in communication with the voltage or current detector to receive information regarding the power quality, the power management controller configured to be in communication with the at least one non-volatile logic controller to provide information effecting storing the machine state to and restoration of the machine state from the plurality of non-volatile logic element arrays;

a voltage regulator connected to receive power from the input power supply and provide power to an output power supply rail configured to provide power to the processing device, wherein the voltage regulator is configured to be in communication with the power management controller and to disconnect the output power supply rail from the input power supply in response to a determination that the power quality is below a threshold;

a charge storage element configured to provide temporary power to the processing device sufficient to power the processing device to store the machine state in the plurality of non-volatile logic element arrays after the output power supply rail is disconnected from the input power supply.

2. The computing device apparatus of claim 1 wherein the power management controller is configured to send a signal to effect stoppage of clocks for the processing device in response to the determination that the power quality is below the threshold.

3. The computing device apparatus of claim 1 wherein the voltage regulator is configured to send a disconnect signal to the power management controller in response to disconnecting the output power supply rail from the input power supply.

4. The computing device apparatus of claim 3 wherein the power management controller is configured to send a backup signal to the at least one non-volatile logic controller in response to receiving the disconnect signal.

5. The computing device apparatus of claim 1 wherein the voltage regulator is configured to detect the power quality'"'"'s rising above the threshold and, in response, to send a good power signal to the power management controller.

8. The computing device apparatus of claim 1 wherein the charge storage element comprises at least one dedicated on-die capacitor.

6. The computing device apparatus of claim 6 wherein the power management controller is configured to send a signal to provide power to the plurality of non-volatile logic element arrays and the at least one non-volatile logic controller to facilitate restoration of the machine state in response to receiving the good power signal.

7. The computing device apparatus of claim 7 wherein the power management controller is configured to determine that power up is complete and, in response, send a signal to effect release of clocks for the processing device wherein the processing device resumes operation from the machine state prior to the determination that the power quality was below the threshold.

9. A method of powering a processing device having a plurality of non-volatile logic element arrays, a plurality of volatile storage elements, and at least one non-volatile logic controller configured to control the plurality of non-volatile logic element arrays to store a machine state represented by the plurality of volatile storage elements and to read out a stored machine state from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements, the method comprising:

providing power from an input power supply to an output power supply rail configured to provide power to the processing device;

a voltage or current detector sensing a power quality from the input power supply;

determining that the power quality is less than a threshold;

in response to determining that the power quality is less than a threshold;

disconnecting the input power supply from the output power supply rail, and

backing up data stored in the plurality of volatile storage elements in a plurality of non-volatile logic element arrays using power from a charge storage element configured to provide temporary power to the processing device sufficient to power the processing device to store the machine state in the plurality of non-volatile logic element arrays after the output power supply rail is disconnected from the input power supply.

10. The method of claim 9 further comprising stopping clocks for the processing device in response to a determination that the power quality is below the threshold.

11. The method of claim 9 further comprising sending a disconnect signal to a power management controller in response to disconnecting the output power supply rail from the input power supply.

12. The method of claim 11 further comprising the power management controller sending a backup signal to the at least one non-volatile logic controller in response to receiving the disconnect signal.

13. The method of claim 9 further comprising detecting the power quality'"'"'s rising above the threshold.

14. The method of claim 13 further comprising a power management controller sending a signal to provide power to the plurality of non-volatile logic element arrays and the at least one non-volatile logic controller to facilitate restoration of the machine state in response to the detecting the power quality'"'"'s rising above the threshold.

15. The method of claim 14 further comprising:

the power management controller detecting that power up is complete and, in response, sending a signal to effect release of clocks for the processing device; and

the processing device resuming operation from the machine state prior to the determination that the power quality was below the threshold.

16. A method of powering a processing device having a plurality of non-volatile logic element arrays, a plurality of volatile storage elements, and at least one non-volatile logic controller configured to control the plurality of non-volatile logic element arrays to store a machine state represented by the plurality of volatile storage elements and to read out a stored machine state from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements, the method comprising:

providing power from an input power supply to an output power supply rail configured to provide power to the processing device;

a voltage or current detector sensing a power quality from the input power supply;

determining that the power quality is less than a threshold;

in response to determining that the power quality is less than a threshold;

disconnecting the input power supply from the output power supply rail,

backing up data stored in the plurality of volatile storage elements in a plurality of non-volatile logic element arrays using power from a charge storage element configured to provide temporary power to the processing device sufficient to power the processing device to store the machine state in the plurality of non-volatile logic element arrays after the output power supply rail is disconnected from the input power supply,

stopping clocks for the processing device,

sending a disconnect signal to a power management controller in response to disconnecting the output power supply rail from the input power supply, and

sending a backup signal to the at least one non-volatile logic controller in response to receiving the disconnect signal;

detecting the power quality'"'"'s rising above the threshold; and

in response to determining the power quality'"'"'s rising above the threshold;

the power management controller sending a signal to provide power to the plurality of non-volatile logic element arrays and the at least one non-volatile logic controller to facilitate restoration of the machine state in response to the detecting the power quality'"'"'s rising above the threshold,

the power management controller detecting that power up is complete and, in response, sending a signal to effect release of clocks for the processing device, and

the processing device resuming operation from the machine state prior to the determination that the power quality was below the threshold.