Erased Page Confirmation in Multilevel Memory

• US 20140075252A1
• Filed: 03/04/2013
• Published: 03/13/2014
• Est. Priority Date: 09/13/2012
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Huang, Jianmin, Avila, Chris Nga Yee, Lee, Dana, Dusija, Gautam Ashok, Luo, Ting
• Granted Patent: US 8,887,011 B2
• Time in Patent Office: Days
• US Class Current: 714/721
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/50004 of threshold voltage

Abstract

In a multi-level cell memory array, a flag that indicates that a logical page is unwritten is subject to a two-step verification. In a first verification step, the logical page is read, and ECC decoding is applied. If the first verification step indicates that the logical page is unwritten, then a second verification step counts the number of cells that are not in an unwritten condition.

Claims

1. A method of verifying a program/erase condition of a logical page of a multilevel flash memory comprising:

reading one or more flag bits that indicate the program/erase condition of the logical page;

in response to determining that the one or more flag bits indicate that the logical page is erased, further verifying the erased condition of the logical page by;

performing a read of the logical page;

performing Error Correction Coding (ECC) analysis of data read from the logical page;

subsequently identifying a number of cells that are not in a state corresponding to the logical page being erased; and

comparing the number of cells that are not in a state corresponding to the logical page being erased with a predetermined number in order to verify the program/erase condition of the logical page.

2. The method of claim 1 wherein the logical page is an upper page and wherein the read of the logical page is performed using two read voltages.

3. The method of claim 2, further comprising, subsequent to performing the ECC analysis, performing a subsequent read.

4. The method of claim 3 wherein the number of cells that are not in a state corresponding to the logical page being erased is identified from the subsequent read.

5. The method of claim 4 wherein the subsequent read is performed using one of the two read voltages.

6. The method of claim 4 wherein the subsequent read is performed using a voltage that is different to both of the two read voltages.

7. The method of claim 1 wherein the ECC analysis of data read from the logical page indicates a pass result.

8. A method of verifying that a logical page in a multi-level cell (MLC) flash memory is unwritten comprising:

in response to determining that a flag indicates that the logical page is unwritten, subsequently performing a read operation on the logical page to obtain verification data;

subsequently performing Error Correction Code (ECC) analysis of the verification data;

if the verification data passes ECC analysis then identifying the logical page as written;

if the verification data fails ECC analysis then determining a number of bits in the logical page that are inconsistent with the logical page being unwritten;

comparing the number with a threshold;

if the number exceeds the threshold then identifying the logical page as written; and

if the number does not exceed the threshold then identifying the logical page as unwritten.

9. The method of claim 8 wherein the logical page is a lower page and the number of bits in the logical page that are inconsistent with the logical page being unwritten is obtained from the verification data.

10. The method of claim 8 wherein the number of bits in the logical page that are inconsistent with the logical page being unwritten is obtained from an additional read operation that is performed subsequent to performing the ECC analysis of the verification data.

11. The method of claim 10 wherein the logical page is an upper page and the additional read operation identifies memory cells in a memory state with the highest threshold voltage range.

12. The method of claim 8 wherein, when the logical page is identified as written, subsequent writing to the logical page is prohibited until after an erase is performed.

13. A multi-level cell (MLC) flash memory system comprising:

an array of flash memory cells arranged in physical pages, each physical page having capacity to store two logical pages of data, a lower page and an upper page;

a plurality of page status flags, each page status flag associated with a logical page;

a read circuit configured to read data from the memory array;

an Error Correction Code (ECC) circuit configured to encode data to be stored in the array of flash memory cells and decode data from the array of flash memory cells, the ECC circuit configured to identify errors in data from the array; and

a page verification circuit configured to verify a page status flag that indicates that a logical page is unwritten by obtaining an indication from the ECC circuit that the logical page is unwritten, and subsequently determining a number of bits within the logical page that are not in an unwritten state, and verifying the logical page as unwritten only if the number is less than a threshold number.

14. The multi-level cell (MLC) flash memory system of claim 13 wherein the read circuit applies a set of read conditions to determining the number of bits within the logical page that are not in an unwritten state.

15. The multi-level cell (MLC) flash memory system of claim 14 wherein the set of read conditions include a discrimination voltage to discriminate between written and unwritten cells.