NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE

• US 20140077285A1
• Filed: 03/18/2013
• Published: 03/20/2014
• Est. Priority Date: 09/19/2012
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: KUNIYA, Takuji, NODA, Homuro
• Application Number:
  US13/845,812
• Publication Number:
  US 20140077285A1
• Time in Patent Office: Days
• US Class Current: 257/324
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

An embodiment includes: a stacked body having an impurity doped silicon layer and an interlayer insulating film alternately stacked on each other in which one layer of the impurity doped silicon layers is replaced with a conductive film enabling forming a metal oxide; a hole penetrating the stacked body in a stacking direction; a channel layer formed in the hole along the stacking direction of the stacked body; a tunnel insulating film formed between an inner surface of the hole and the channel layer; a charge trapping layer formed between the inner surface of the hole and the tunnel insulating film; and a block insulating film formed between the inner surface of the hole and the charge trapping layer.

Claims

1. A non-volatile semiconductor memory device comprising:

a stacked body having an impurity doped silicon layer and an interlayer insulating film alternately stacked on each other in which one layer of the impurity doped silicon layers is replaced with a conductive film enabling forming a metal oxide;

a hole penetrating the stacked body in a stacking direction;

a channel layer formed in the hole along the stacking direction of the stacked body;

a tunnel insulating film formed between an inner surface of the hole and the channel layer;

a charge trapping layer formed between the inner surface of the hole and the tunnel insulating film; and

a block insulating film formed between the inner surface of the hole and the charge trapping layer.

2. The non-volatile semiconductor memory device according to claim 1, wherein the conductive film is replaced with a topmost impurity doped silicon layer of the stacked body.

3. The non-volatile semiconductor memory device according to claim 1, wherein the conductive film is a metal or a metal compound.

4. The non-volatile semiconductor memory device according to claim 1, wherein the conductive film is selected from Ti, TiN, Al, and AlN.

5. The non-volatile semiconductor memory device according to claim 1, wherein the metal oxide is TiO_x or Al_xO_y (x and y are positive integers).

6. The non-volatile semiconductor memory device according to claim 1, wherein:

a plurality of memory cells is three-dimensionally disposed on the stacked body;

cell transistors included in the memory cell are connected in series in a height direction to form a NAND string;

two rows of the NAND strings in a same row form a string unit; and

a plurality of string units arranged in a column direction forms a block.

7. The non-volatile semiconductor memory device according to claim 6, comprising:

a bit line that selects the NAND string in the column direction;

a word line shared for individual cell layers between NAND strings in different rows sharing a same bit line; and

a select transistor provided on the individual NAND strings to select the NAND string in a row direction.

8. The non-volatile semiconductor memory device according to claim 7, wherein:

a memory cell array is formed of a plurality of blocks arranged in the column direction;

the bit line is shared between the blocks; and

the word line is separated between the blocks.

9. A method for manufacturing a non-volatile semiconductor memory device comprising the steps of:

forming a stacked body having an impurity doped silicon layer and an interlayer insulating film alternately stacked on each other in which one layer of the impurity doped silicon layers is replaced with a conductive film enabling forming a metal oxide;

forming a mask pattern formed with an opening on the stacked body;

processing the stacked body through the opening to form a hole penetrating the stacked body in a stacking direction;

forming a block insulating film on an inner surface of the hole;

forming a charge trapping layer on a surface of the block insulating film in the hole;

forming a tunnel insulating film on a surface of the charge trapping layer in the hole; and

forming a channel layer on a surface of the tunnel insulating film in the hole.

10. The method for manufacturing a non-volatile semiconductor memory device according to claim 9, wherein the conductive film is etched in forming the hole in the stacked body, and a protective film made of the metal oxide is formed on a side wall of the opening.

11. The method for manufacturing a non-volatile semiconductor memory device according to claim 9, wherein the conductive film is replaced with a topmost impurity doped silicon layer of the stacked body.

12. The method for manufacturing a non-volatile semiconductor memory device according to claim 9, wherein the conductive film is a metal or a metal compound.

13. The method for manufacturing a non-volatile semiconductor memory device according to claim 9, wherein the conductive film is selected from Ti, TiN, Al, and AlN.

14. The method for manufacturing a non-volatile semiconductor memory device according to claim 9, wherein the metal oxide is TiO_x or Al_xO_y (x and y are positive integers).

15. A method for manufacturing a non-volatile semiconductor memory device comprising the steps of:

forming a stacked body having an impurity doped silicon layer and an impurity non-doped silicon layer alternately stacked on each other in which one layer of the impurity doped silicon layers is replaced with a conductive film enabling forming a metal oxide;

forming a mask pattern formed with an opening on the stacked body;

processing the stacked body through the opening to form a hole penetrating the stacked body in a stacking direction;

removing the impurity non-doped silicon layer formed with the hole;

filling an interlayer insulating film in a space from which the impurity non-doped silicon layer is removed;

forming a block insulating film on an inner surface of the hole;

forming a charge trapping layer on a surface of the block insulating film in the hole;

forming a tunnel insulating film on a surface of the charge trapping layer in the hole; and

forming a channel layer on a surface of the tunnel insulating film in the hole.

16. The method for manufacturing a non-volatile semiconductor memory device according to claim 15, wherein the conductive film is etched in forming the hole in the stacked body, and a protective film made of the metal oxide is formed on a side wall of the opening.

17. The method for manufacturing a non-volatile semiconductor memory device according to claim 15, wherein the conductive film is replaced with a topmost impurity doped silicon layer of the stacked body.

18. The method for manufacturing a non-volatile semiconductor memory device according to claim 15, wherein the conductive film is a metal or a metal compound.

19. The method for manufacturing a non-volatile semiconductor memory device according to claim 15, wherein the conductive film is selected from Ti, TiN, Al, and AlN.

20. The method for manufacturing a non-volatile semiconductor memory device according to claim 15, wherein the metal oxide is TiO_x or Al_xO_y (x and y are positive integers).