Matrix Lid Heatspreader for Flip Chip Package

• US 20140077352A1
• Filed: 09/14/2012
• Published: 03/20/2014
• Est. Priority Date: 09/14/2012
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Leal, George R., Pham, Tim V.
• Granted Patent: US 9,159,643 B2
• Time in Patent Office: Days
• US Class Current: 257/704
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/566 Release layers for moulds, e.g. release layers, layers against residue during moulding
• CPC Class Codes: H01L 2223/54486 Located on package parts, e.g. encapsulation, leads, package substrate
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/29191 The principal constituent being an elastomer, e.g. silicones, isoprene, neoprene
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/83191 wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/92225 the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3675 characterised by the shape of the housing
• CPC Class Codes: H01L 23/3736 Metallic materials H01L23/3732, H01L23/3733, H01L23/3735, H01L23/3737, H01L23/3738 take precedence
• CPC Class Codes: H01L 23/4334 Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 23/49568 : specifically adapted to facilitate heat dissipation
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/141 : Analog devices
• CPC Class Codes: H01L 2924/14335 : Digital signal processor [DSP]
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/17738 : the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
• CPC Class Codes: H01L 2924/17747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A method and apparatus are provided for manufacturing a lead frame based thermally enhanced flip chip package with an exposed heat spreader lid array (310) designed for direct attachment to an array of integrated circuit die (306) by including a thermal interface adhesion layer (308) to each die (306) and encapsulating the attached heat spreader lid array (310) and array of integrated circuit die (306) with mold compound (321) except for planar upper lid surfaces of the heat spreader lids (312).

Claims

1. A method of making a plurality of integrated circuit packages, comprising:

providing a substrate array comprising a plurality of flip chip mounted integrated circuit die, each having a first surface that is attached to a first surface of the substrate array using flip chip bumps and a second surface which is formed a compliant thermally conductive interface layer;

providing a heat spreader lid array comprising a plurality of heat spreader lids having planar upper lid surfaces connected together by connection spars to define one or more openings between adjacent heat spreader lids defining singulation cut areas around each head spreader lid;

attaching the heat spreader lid array to the substrate array by pressing the heat spreader lid array to compress the compliant thermally conductive interface layer formed on each integrated circuit die to expand laterally to form a compressed thermally conductive interface layer which completely covers the second surface of the die and make direct contact therebetween;

encapsulating the plurality of flip chip mounted integrated circuit die and the heat spreader lid array with encapsulant wherein the upper planar upper lid surfaces of the plurality of heat spreader lids are exposed; and

curing the encapsulant to form an array of molded packages, each having a portion of the substrate array exposed on a first side and a planar upper lid surface of a heat spreader lid exposed on a second side.

2. The method of claim 1, further comprising:

singulating the array of molded packages into a plurality of integrated circuit packages.

3. The method of claim 1, further comprising:

forming a plurality of ball grid arrays on an exposed surface of said substrate array to be electrically connected to conductive traces formed in the substrate array.

4. The method of claim 1, further comprising forming the compliant thermally conductive interface layer by applying a thermally conductive, compliant adhesive layer or patterned layer of compliant, thermally conductive grease or non-curing silicon material to the second surface of each integrated circuit die.

5. The method of claim 1, where providing the heat spreader lid array comprises selectively etching, machining, or stamping a metal layer to define a planar leadframe heat spreader lid array with the plurality of heat spreader lids and connection spars formed in a single planar layer.

6. The method of claim 1, where providing the heat spreader lid array comprises providing a plurality of upset heat spreader lids connected together by a plurality of downset lead finger spars to define the one or more openings between adjacent heat spreader lids.

7. The method of claim 1, where attaching the heat spreader lid array to the substrate array comprises pressing an upper mold cavity tool against a lower mold cavity tool and the planar upper lid surfaces of the heat spreader lid array to form a mold cavity between the upper and lower mold cavity and to attach the heat spreader lid array into contact with the thermally conductive interface layer formed on each integrated circuit die.

8. The method of claim 7, further comprising lining an interior surface of the upper mold cavity with a polymer film before pressing the upper mold cavity tool against the lower mold cavity tool.

9. The method of claim 7, where encapsulating the plurality of flip chip mounted integrated circuit die and the heat spreader lid array with encapsulant comprises:

filling the mold cavity with encapsulant except for the planar upper lid surfaces of the plurality of heat spreader lids; and

clamping the upper and lower mold cavity tools.

10. The method of claim 1, where providing the heat spreader lid array comprises providing a the plurality of upset heat spreader lids connected together by a plurality of downset lead finger spars, where each upset heat spreader lid is sized to make contact with a corresponding integrated circuit die through the compliant thermally conductive interface layer formed thereon.

11. A semiconductor package, comprising:

a substrate having first and second surfaces;

a die having first and second surfaces, where the first surface of the die is flip-chip bonded to the first surface of the substrate;

a thermally conductive interface layer formed to cover the second surface of the die; and

a heat spreader lid comprising an exposed heat dissipation surface layer and a plurality of connection spars extending laterally from the heat dissipation surface layer, where the heat dissipation surface layer contacts the thermally conductive interface layer and is positioned apart from the substrate to define an encapsulation molding region in which encapsulation mold compound material is located to permanently attach the substrate, die, and heat spreader lid.

12. The semiconductor package of claim 11, where the plurality of connection spars extend laterally to be co-planar with the exposed heat dissipation surface layer.

13. The semiconductor package of claim 11, where the plurality of connection spars extend laterally as downset connection spars that are not co-planar with the exposed heat dissipation surface layer.

14. The semiconductor package of claim 11, where the heat spreader lid is formed with a thermally conductive layer of copper, nickel or an alloy thereof.

15. The semiconductor package of claim 11, where the exposed heat dissipation surface layer has a thermal contact surface that is at least as large as the second surface of the die.

16. The semiconductor package of claim 11, further comprising an array of solder balls attached to the second surface of the substrate to make electrical connection to the die via conductive traces formed in the substrate.

17. The semiconductor package of claim 11, where the plurality of connection spars are embedded and surrounded by the encapsulation mold compound material except at peripheral side ends of the semiconductor package.

18. A method of making a semiconductor package, comprising:

attaching a plurality of integrated circuit die to a molded array package substrate array using flip-chip bonding to enable electrical connection between each integrated circuit die and conductors in the substrate array;

providing a heat spreader lid array formed with an unlaminated thermally conductive material to define a plurality of heat spreader lids positioned for alignment with the plurality of integrated circuit die, where each heat spread lid comprises an exposed heat dissipation surface layer and a plurality of connection spars extending laterally from the exposed heat dissipation surface layer;

forming a compression-compliant thermal interface material layer on an exposed first surface of each of the plurality of integrated circuit die or on a bottom surface of each exposed heat dissipation surface layer;

pressing the heat spreader lid array into direct thermal contact with the plurality of integrated circuit die by compressing the compression-compliant thermal interface material layer to laterally expand to completely cover the first surface of each integrated circuit die and to define an encapsulation molding cavity region between the exposed heat dissipation surface layers and the substrate array;

filling the encapsulation molding cavity region with encapsulation mold compound material without covering the exposed heat dissipation surface layers with encapsulation mold compound material;

curing the encapsulation mold compound material in the encapsulation molding cavity region to encapsulate the plurality of integrated circuit die and to seal the substrate array and heat spreader lid array, resulting in an array of molded packages, each having a portion of the heat spreader lid array exposed on a first side.

19. The method of claim 18, further comprising:

singulating the array of molded packages into a plurality of integrated circuit packages.

20. The method of claim 18, wherein the heat spreader lid array includes each exposed heat dissipation surface layer and connection spars extending laterally and formed in a single planar layer with said exposed heat dissipation surface layer.