DATA READOUT CIRCUIT OF PHASE CHANGE MEMORY

• US 20140078820A1
• Filed: 06/24/2011
• Published: 03/20/2014
• Est. Priority Date: 06/07/2011
• Status: Active Grant

• Current Assignee: Shanghai Institute of Microsystem and Information Technology Chinese Academy of Sciences (Chinese Academy of Sciences)
• Original Assignee: Shanghai Institute of Microsystem and Information Technology Chinese Academy of Sciences (Chinese Academy of Sciences)
• Inventors: Song, Zhitang, Li, Xi, Chen, Houpeng, Cai, Daolin
• Granted Patent: US 8,947,924 B2
• Time in Patent Office: Days
• US Class Current: 365/163
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0026 Bit-line or column circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell

Abstract

A data readout circuit of phase change memory, relating to one or more phase change memory cells, wherein each phase change memory cell is connected to the control circuit by bit line and word line; said data readout circuit comprises: a clamp voltage generating circuit, used to generate a clamp voltage; a precharge circuit, used to fast charge bit line under the control of a clamp voltage; a clamped current generating circuit, used to generate a clamped current to keep bit line at clamped state under the control of a clamp voltage; a clamped current operation circuit, used to perform subtraction and multiplication on clamped current to increase the difference of clamped current between high resistance state and low resistance state; a sense amplifier circuit, used to compare the operated clamped current and the reference current and output the readout result. Compared with the prior art, the data readout circuit of phase change memory provided by the present invention can effectively enhance the data readout speed, decrease the misreading window between high resistance state and low resistance state, reduce the crosstalk of data readout, and improve the reliability of data readout.

Claims

1. A data readout circuit of phase change memory, wherein said phase change memory comprises one or more phase change memory cells and each phase change memory cell is connected to the control circuit by bit line and word line;

characterized in that said data readout circuit comprises;

a clamp voltage generating circuit, used to generate a clamp voltage;

a precharge circuit, used to fast charge bit line of said memory cells under the control of said clamp voltage;

a clamped current generating circuit, used to generate a clamped current to keep said bit line at clamped state under the control of said clamp voltage;

a clamped current operation circuit, used to perform subtraction and multiplication on said clamped current to increase the difference of clamped current between high resistance state and low resistance state;

a sense amplifier circuit, used to compare the clamped current operated by said clamped current operation circuit and the reference current and output the readout result.

2. The data readout circuit of phase change memory according to claim 1, characterized by further comprising a transfer gate connected in series on said bit line, used to connect said precharge circuit and said clamped current generating circuit to said bit line through said transfer gate.

3. The data readout circuit of phase change memory according to claim 1, characterized by further comprising a discharge circuit, used to discharge the remaining charge from said bit line and from load terminal of said data readout circuit after said sense amplifier circuit completes comparison amplification.

4. The data readout circuit of phase change memory according to claim 3, characterized in that said discharge circuit comprises a controlled first nMOS transistor connected between said precharge circuit and ground wire and a controlled second nMOS transistor connected between said bit line and ground wire.

5. The data readout circuit of phase change memory according to claim 1, characterized in that said clamp voltage generating circuit comprises a current source, a first nMOS transistor connected in the form of a diode, and a second nMOS transistor connected in series to the first nMOS transistor, wherein the drain of the first nMOS transistor is connected to the current output terminal of said current source, the gate of the first nMOS transistor is connected to the gate of the second nMOS transistor, the source of the first nMOS transistor is connected to the drain of the second nMOS transistor, and the source of the second nMOS transistor is connected to the ground.

6. The data readout circuit of phase change memory according to claim 1, characterized in that said precharge circuit comprises a precharge switching transistor and a precharge clamp nMOS transistor connected in series to said precharge switching transistor.

7. The data readout circuit of phase change memory according to claim 1, characterized in that said clamped current generating circuit comprises a clamp nMOS transistor.

8. The data readout circuit of phase change memory according to claim 1, characterized in that said clamped current operation circuit comprises two current mirror configurations formed by four pMOS transistors, wherein the gate of the first pMOS transistor is connected to the gate of the second pMOS transistor with the gate of the first pMOS transistor connected to the drain of the first pMOS transistor, the drain of the first pMOS transistor is connected to the bias current source, the source of the first pMOS transistor is connected to a voltage source, the source of the second pMOS transistor is connected to a voltage source, and the drain of the second pMOS transistor is connected to said clamped current generating circuit;

the gate of the third pMOS transistor is connected to the gate of the fourth pMOS transistor with the gate of the third pMOS transistor connected to the drain of the third pMOS transistor, the drain of the third pMOS transistor connected to said clamped current generating circuit, the source of the third pMOS transistor connected to a voltage source, the source of the fourth pMOS transistor is connected to a voltage source, and the drain of the fourth pMOS transistor outputs the operated current;

the current mirror formed by first pMOS transistor and the second pMOS transistor provides a bias current, the second pMOS transistor and the third pMOS transistor perform subtraction, and the third pMOS transistor and the fourth pMOS transistor perform multiplication.

9. The data readout circuit of phase change memory according to claim 8, characterized in that said clamped current generating circuit comprises a clamp nMOS transistor, and the drain of said clamp nMOS transistor is connected to the drain of the second pMOS transistor and the drain of the third pMOS transistor.

10. The data readout circuit of phase change memory according to claim 1, characterized in that said sense amplifier circuit comprises a current comparator, wherein the input terminal of said current comparator inputs said clamped current and said reference current respectively, and the output terminal of said current comparator outputs the comparison result of the two currents mentioned above.