MULTIPLEXING AND DEMULTIPLEXING DATA

• US 20140079078A1
• Filed: 11/25/2013
• Published: 03/20/2014
• Est. Priority Date: 04/29/2008
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Nistor, Adrian Ioan, Pelly, Jason
• Granted Patent: US 8,902,748 B2
• Time in Patent Office: Days
• US Class Current: 370/535
• CPC Class Codes: H04J 3/02 Details electronic switching or gating H03K17/00
• CPC Class Codes: H04J 3/047 Distributors with transistors or integrated circuits

Abstract

Apparatus arranged to perform data multiplexing or demultiplexing or a non-transitory computer readable medium comprising a computer program which, when executed by a computer, carries out a method of multiplexing or demultiplexing data, the apparatus comprising a memory, an interface, and a processing unit arranged to determine locations of corresponding regions of the memory for corresponding channels based on data sizes and time-unit-numbers that have passed since a previous corresponding quantity of channel data for a corresponding channel was last stored in the memory or processed, wherein the data sizes and time-unit numbers correspond to one or more channels of the plurality of channels, such that the processing unit will not store the corresponding quantity of the channel data, for each corresponding channel of the plurality of channels, at a location in the memory that is currently storing any channel data that has not yet been output or processed.

Claims

1. Apparatus arranged to perform data demultiplexing, the apparatus comprising:

an interface arranged to receive, during each of a series of time-units, multiplexed data, wherein the multiplexed data comprises, for each corresponding channel of a plurality of channels, a corresponding quantity of channel data of a corresponding data size;

a memory; and

a processing unit coupled to the interface and to the memory, the processing unit arranged to store, during each of the series of time-units, for each corresponding channel of the plurality of channels, the corresponding quantity of the channel data received during a corresponding time-unit of the time-units in a contiguous region of the memory associated with the corresponding channel, wherein each of the plurality of channels has a corresponding time-unit-number of time-unit-numbers such that, for each corresponding channel of the plurality of channels, the corresponding quantity of the channel data stored in the corresponding region of the memory for the corresponding channel is to be processed after a number of the time-units equal to the time-unit-number for the corresponding channel has passed since a previous corresponding quantity of the channel data for the corresponding channel was last processed, the processing unit further arranged to determine locations of the regions of the memory based on the data sizes and the time-unit-numbers corresponding to one or more channels from the plurality of channels such that the processing unit will not store the corresponding quantity of the channel data at a location in the memory that is currently storing any channel data that has not yet been processed.

2. The apparatus according to claim 1, in which the processor is further arranged, for determining the locations of the regions of the memory, to determine a first location of a first region of the memory for a first channel prior to determining a second location of a second region of the memory for a second channel if a first time-unit-number corresponding to the first channel is greater than a second time-unit-number corresponding to the second channel.

3. The apparatus according claim 1, in which the processor is further arranged to determine the locations of the regions of the memory so that there are substantially no gaps between the regions of the memory within the memory.

4. The apparatus according to claim 1, in which the processor is further arranged to determine the locations of the regions of the memory so that at least two of the regions of the memory overlap.

5. The apparatus according to claim 1, in which the processor is further arranged to repeat the determining of the locations of the regions of the memory to update one or more of the locations of one or more of the regions of the memory.

6. The apparatus according to claim 5, in which the processor is further arranged to determine whether the one or more of the locations of the one or more of the regions of the memory should be updated during a current time-unit of the time-units.

7. The apparatus according to claim 6, wherein one of the one or more of the locations of one of the one or more regions of the memory corresponding to a selected channel is to be updated during a scheduled time-unit in which selected channel data stored in the memory for the selected channel is processed, the processor being further arranged to update the one of the one or more locations of the one of the one or more regions of the memory after the selected channel data is processed.

8. The apparatus according to claim 6, wherein one of the one or more of locations of one of the one or more regions of the memory corresponding to a selected channel is to be updated during a scheduled time-unit in which selected channel data is stored in the memory for the selected channel, the processor being further arranged to update the one of the one or more locations of the one of the one or more regions of the memory before the selected channel data is stored in the memory.

9. The apparatus according to claim 1, in which, for each corresponding channel of the plurality of channels, a corresponding time-unit-number for the corresponding channel is a positive integer multiple of each corresponding time-unit-number for each other channel of the plurality of channels.

10. Apparatus arranged to perform data multiplexing, the apparatus comprising:

a memory;

an interface; and

a processing unit coupled to the memory and to the interface, the processing unit arranged to form, during each of a series of time-units, multiplexed data by outputting via the interface, for each corresponding channel of a plurality of channels, a corresponding quantity of channel data of a corresponding data size of data sizes that is being stored in the memory, wherein each of the plurality of channels has a corresponding time-unit-number of time-unit-numbers, the processing unit further arranged to store, for each corresponding channel of the plurality of channels, the corresponding quantity of the channel data in a corresponding region of regions of the memory for the corresponding channel after a number of the time-units equal to the corresponding time-unit-number for the corresponding channel has passed since a previous corresponding quantity of the channel data for the corresponding channel was last stored in the memory, the processing unit further arranged to determine locations of the regions of the memory based on the data sizes and the time-unit-numbers corresponding to one or more channels of the plurality of channels such that the processing unit will not store the corresponding quantity of the channel data at a location in the memory that is currently storing any channel data that has not yet been output.

11. The apparatus according to claim 10, in which the processor is further arranged, for determining the locations of the regions of the memory, to determine a first location of a first region of the memory for a first channel prior to determining a second location of a second region of the memory for a second channel if a first time-unit-number corresponding to the first channel is greater than a second time-unit-number corresponding to the second channel.

12. The apparatus according claim 11, in which the processor is further arranged to determine the locations of the regions of the memory so that there are substantially no gaps between the regions of the memory within the memory.

13. The apparatus according claim 10, in which the processor is further arranged to determine the locations of the regions of the memory so that there are substantially no gaps between the regions of the memory within the memory.

14. The apparatus according to claim 10, in which the processor is further arranged to determine the locations of the regions of the memory so that at least two of the regions of the memory overlap.

15. The apparatus according to claim 10, in which the processor is further arranged to repeat the determining the locations of the regions of the memory to update one or more of the locations of one or more of the regions of the memory.

16. The apparatus according to claim 15, in which the processor is further arranged to determine whether the one or more locations of one or more of the regions of the memory should be updated during a current time-unit of the time-units.

17. The apparatus according to claim 16, wherein one of the one or more of the locations of the one of the one or more regions of the memory corresponding to a selected channel is to be updated during a scheduled time-unit in which selected channel data stored in the memory for the selected channel is processed, the processor being further arranged to update the one of the one or more locations of the one of the one or more regions of the memory after the selected channel data is processed.

18. The apparatus according to claim 16, wherein one of the one or more locations of one of the one or more regions of the memory corresponding to a selected channel is to be updated during a scheduled time-unit in which selected channel data is stored in the memory for the selected channel, the processor being further arranged to update the one of the one or more locations of the one of the one or more regions of the memory before the selected channel data is stored in the memory.

19. The apparatus according to claim 10, in which, for each corresponding channel of the plurality of channels, a corresponding time-unit-number for the corresponding channel is a positive integer multiple of each corresponding time-unit-number for each other channel of the plurality of channels.

20. A non-transitory computer readable medium comprising a computer program which, when executed by a computer, carries out a method of multiplexing data, the method comprising:

during each of a series of time-units, forming multiplexed data by outputting, for each corresponding channel of a plurality of channels, a corresponding quantity of channel data of a corresponding data size of data sizes that is being stored in a memory;

wherein each corresponding channel of the plurality of channels has a corresponding time-unit-number of time-unit-numbers, for each corresponding channel of the plurality of channels, storing the corresponding quantity of the channel data in a corresponding region of regions of the memory for the corresponding channel after a number of the time units equal to the corresponding time-unit-number for the corresponding channel has passed since a previous corresponding quantity of the channel data for the corresponding channel was last stored in the memory;

determining locations of the regions of the memory based on the data sizes and the time-unit-numbers corresponding to one or more channels of the plurality of channels such that the step of storing will not store the corresponding quantity of the channel data at a location in the memory that is currently storing any channel data that has not yet been output.