SHIFTING REGISTER UNIT, SHIFTING REGISTER, DISPLAY APPARATUS AND DRIVING METHOD THEREOF
First Claim
1. A shifting register unit, comprising:
- a storage capacitor, having a terminal connected to a pull-up node, and another terminal connected to an output terminal;
a first thin-film transistor, for charging the pull-up node and the storage capacitor when an input signal is at high-level;
a reset module, for discharging the pull-up node and the storage capacitor under the control of a reset signal;
a third thin-film transistor, for sending an output signal to the output terminal when a first clock signal is at high-level;
an eighth thin-film transistor, for sending a trigger signal when the third thin-film transistor sends the output signal to the output terminal; and
a potential maintaining module, for alternately controlling a pull-down node to be at high-level before an arrival of a next input signal according to the first clock signal and a second clock signal, to make the pull-up node and the output terminal continue to be discharged.
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Accused Products
Abstract
The embodiments of the present invention provide a shifting register unit, a shifting register, a display apparatus and a driving method thereof, which can solve the problem that the displaying lines close to the bottom of a display panel can not operate normally due to the accumulation of the delays present in the existing shifting register unit and the problem that the lifespan of the third thin-film transistor is affected by the frequent switching-on thereof. The technical solutions allows the trigger signal of the (n+1)th shifting register unit stage to be provided by the first clock signal transmitted from the INPUT_NEXT terminal of the nth shifting register stage, and it can avoid the delay due to the trigger signal of the (n+1)th shifting register unit stage being provided by an output signal of the nth shifting register unit stage, and it can solve the technical problem that the display lines close to the bottom of the display panel can not operate normally due to the accumulation of the delays. Further, after the nth shifting register unit stage outputs the output signal and before the next input signal arrives, the pull-down node remains at high-level under the alternating control of the two clock signals. Thereby, it can be ensured that the pull-up node PU and the output terminal continue to be discharged, and thus the problem that the lifespan of the third thin-film transistor is affected by the frequent switching-on thereof can be solved.
63 Citations
10 Claims
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1. A shifting register unit, comprising:
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a storage capacitor, having a terminal connected to a pull-up node, and another terminal connected to an output terminal; a first thin-film transistor, for charging the pull-up node and the storage capacitor when an input signal is at high-level; a reset module, for discharging the pull-up node and the storage capacitor under the control of a reset signal; a third thin-film transistor, for sending an output signal to the output terminal when a first clock signal is at high-level; an eighth thin-film transistor, for sending a trigger signal when the third thin-film transistor sends the output signal to the output terminal; and a potential maintaining module, for alternately controlling a pull-down node to be at high-level before an arrival of a next input signal according to the first clock signal and a second clock signal, to make the pull-up node and the output terminal continue to be discharged. - View Dependent Claims (2, 3, 4, 5, 7, 8, 9, 10)
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6. (canceled)
Specification