PROVIDING AN ASYMMETRIC MULTICORE PROCESSOR SYSTEM TRANSPARENTLY TO AN OPERATING SYSTEM

• US 20140082630A1
• Filed: 12/30/2011
• Published: 03/20/2014
• Est. Priority Date: 12/30/2011
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Ginzburg, Boris, Osadchiy, Ilya, Ronen, Ronny, Weissmann, Eliezer, Mishaeli, Michael, Naveh, Alon, Koufaty, David A., Hahn, Scott D., Li, Tong, Abu-Salah, Hisham, Narvaez, Paolo, Jaleel, Aamer, Rotem, Efraim, Yosef, Yuval, Aggarwal, Anil, Mendleson, Avi, Gorbatov, Eugene, Subbareddy, Dheeraj R., Van Craeynest, Kenzo
• Granted Patent: US 9,720,730 B2
• Time in Patent Office: Days
• US Class Current: 718/105
• CPC Class Codes: G06F 15/7807 System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/4856 resumption being on a different machine, e.g. task migration, virtual machine migration G06F9/5088 takes precedence
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In one embodiment, the present invention includes a multicore processor with first and second groups of cores. The second group can be of a different instruction set architecture (ISA) than the first group or of the same ISA set but having different power and performance support level, and is transparent to an operating system (OS). The processor further includes a migration unit that handles migration requests for a number of different scenarios and causes a context switch to dynamically migrate a process from the second core to a first core of the first group. This dynamic hardware-based context switch can be transparent to the OS. Other embodiments are described and claimed.

Claims

1. A multicore processor including:

a core of a first instruction set architecture (ISA), the first ISA core visible to an operating system (OS) and including a first use register to store an indicator to identify an ISA used by a process executing on the first ISA core;

a core of a second ISA including a second use register to store an indicator to identify an ISA used by a process executing on the second ISA core, wherein the second ISA core is transparent to the OS and heterogeneous from the first ISA core; and

a migration unit coupled to the first and second ISA cores to dynamically migrate a first process scheduled by the OS to the first ISA core to the second ISA core, where the dynamic migration is transparent to the OS.

2. The multicore processor of claim 1, wherein the migration unit is to dynamically migrate the first process based at least in part on the indicator stored in the first use register of the first ISA core.

3. The multicore processor of claim 2, wherein the migration unit is to dynamically migrate the first process further based on performance monitor information obtained during execution of the first process on the first core.

4. The multicore processor of claim 1, wherein the migration unit includes a state storage to store a portion of a state of the first ISA core after the dynamic migration, wherein the state portion does not have a corresponding state storage in the second ISA core.

5. The multicore processor of claim 1, further comprising a process profile table to store a plurality of entries each associated with a process and including a field to indicate an ISA used by the process.

6. The multicore processor of claim 5, wherein the migration unit is to access the process profile table and to dynamically migrate a process scheduled to the first ISA core by the OS to the second ISA core based at least in part on the entry field.

7. The multicore processor of claim 6, wherein the migration unit includes an exception handling unit to handle an exception occurring during execution of the process on the second ISA core transparently to the OS.

8. The multicore processor of claim 5, wherein the first ISA core includes a register array including the first use register, a first supported register including a plurality of fields each to indicate whether a corresponding hardware feature is supported by the first ISA core, and a first enabled register including a plurality of fields each to indicate whether a corresponding hardware feature is enabled for execution of the first process.

9. The multicore processor of claim 1, wherein the migration unit includes a first counter to count a number of times the first process has been switched between the first ISA core and the second ISA core.

10. The multicore processor of claim 9, wherein the migration unit is to prevent migration of the first process from the first ISA core to the second ISA core when a value of the first counter is greater than a first threshold.

11. A method comprising:

determining, in a migration unit of a multicore processor, if code of a process executing on a first core is supported by a second core, wherein the first and second cores are of the multicore processor and the second core is transparent to an operating system (OS) and heterogeneous from the first core; and

if so, dynamically migrating the process from the first core to the second core, via the migration unit, if the first core is underutilized.

12. The method of claim 11, further comprising determining whether the process has switched between the first core and the second core greater than a threshold number of times and dynamically migrating the process to the first core transparently to the OS if the process has been switched less than the threshold number of times.

13. The method of claim 12, further comprising maintaining the process on the first core if the process has been switched between the first core and the second core greater than the threshold number of times.

14. The method of claim 11, further comprising accessing a use register of the first core to determine if the code is supported by the second core, the use register to store a field to indicate an ISA used by the code.

15. The method of claim 11, further comprising waking the migration unit responsive to a synchronous event to determine if the code is supported by the second core.

16. The method of claim 11, further comprising waking the migration unit responsive to an asynchronous event.

17. The method of claim 16, further comprising dynamically migrating the process from the second core to the first core transparently to the OS responsive to the asynchronous event.

18. The method of claim 12, further comprising dynamically migrating the process from the second core to the first core if a utilization level of the second core is higher than a threshold level.

19. A system comprising:

a multicore processor including a first plurality of cores and a second plurality of cores, the second plurality of cores heterogeneous to the first plurality of cores and transparent to an operating system (OS), and a migration unit, wherein the migration unit is to receive an interrupt from a second core of the second plurality of cores responsive to an instruction of a process that the second core does not support and to cause a context switch to dynamically migrate the process from the second core to a first core of the first plurality of cores transparently to the OS, wherein the OS scheduled the process to the first core; and

a dynamic random access memory (DRAM) coupled to the multicore processor.

20. The system of claim 19, wherein the migration unit includes a hardware exception unit to handle an exception caused by the instruction of the process that the second core does not support transparently to the OS.

21. The system of claim 19, wherein the migration unit includes:

a hardware context switch logic to cause a second process executing on the first core to dynamically switch to the second core transparently to the OS; and

a state storage to store a portion of state of the second process during execution of the second process on the second core.

22. The system of claim 19, wherein the migration unit includes a process profile table to store a plurality of entries each associated with a process and including a field to indicate an ISA used by the process, the migration unit to access the process profile table and to dynamically migrate the process to the second core based at least in part on the field of the entry for the process.

23. The system of claim 19, wherein the migration unit includes a counter to count a number of switches of the process between the first and second cores, wherein the migration unit is to prevent a context switch between the first core and the second core if the number of switches exceeds a threshold.

24. The system of claim 19, wherein the second plurality of cores is of a different instruction set architecture (ISA) than the first plurality of cores.

25. The system of claim 24, wherein the different ISA is partially overlapping with an ISA of the first plurality of cores.

26. The system of claim 19, wherein the second plurality of cores is of a different performance and/or power level than the first plurality of cores.