NON-PLANAR SEMICONDUCTOR DEVICE HAVING CHANNEL REGION WITH LOW BAND-GAP CLADDING LAYER

• US 20140084239A1
• Filed: 09/27/2012
• Published: 03/27/2014
• Est. Priority Date: 09/27/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Radosavljevic, Marko, Dewey, Gilbert, Chu-Kung, Benjamin, Suri, Satyarth, Pillarisetty, Ravi, Mukherjee, Niloy, Then, Han Wui, Chau, Robert S., Basu, Dipanjan, Gardner, Sanaz K.
• Granted Patent: US 8,785,909 B2
• Time in Patent Office: Days
• US Class Current: 257/12
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/068 comprising a junction
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/201 including two or more compounds , e.g. alloys H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66469 with one- or zero-dimensional channel, e.g. quantum wire field-effect transistors, in-plane gate transistors [IPG], single electron transistors [SET], Coulomb blockade transistors, striped channel transistors
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Non-planar semiconductor devices having channel regions with low band-gap cladding layers are described. For example, a semiconductor device includes a vertical arrangement of a plurality of nanowires disposed above a substrate. Each nanowire includes an inner region having a first band gap and an outer cladding layer surrounding the inner region. The cladding layer has a second, lower band gap. A gate stack is disposed on and completely surrounds the channel region of each of the nanowires. The gate stack includes a gate dielectric layer disposed on and surrounding the cladding layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the channel regions of the nanowires.

Claims

1. A semiconductor device, comprising:

a vertical arrangement of a plurality of nanowires disposed above a substrate, each nanowire horizontally oriented with respect to the substrate and each nanowire comprising an inner region having a first band gap and an outer cladding layer surrounding the inner region, the cladding layer having a second, narrower band gap;

a gate stack disposed on and completely surrounding a channel region of each of the nanowires, the gate stack comprising a gate dielectric layer disposed on and surrounding the cladding layer and a gate electrode disposed on the gate dielectric layer; and

source and drain regions disposed on either side of the channel regions of the nanowires.

2. The semiconductor device of claim 1, wherein the cladding layer comprises a material suitable to propagate a wave-function with low resistance.

3. The semiconductor device of claim 2, wherein the inner region of each channel region comprises a material suitable to substantially prevent current flow from source regions to drain regions.

4. The semiconductor device of claim 1, wherein material pairs of the cladding layer and inner region are selected from the group consisting of InP/InGaAs, GaAs/AlGaAs and AlInSb/InSb.

5. The semiconductor device of claim 1, wherein the cladding layer is germanium-rich and the inner region is silicon-rich.

6. The semiconductor device of claim 1, wherein the cladding layer has a thickness suitable to propagate a substantial portion of a wave-function and to inhibit a significant portion of the wave-function from entering the inner region of each channel region.

7. The semiconductor device of claim 6, wherein the cladding layer has a thickness approximately in the range of 50-100 Angstroms.

8. The semiconductor device of claim 1, wherein the source and drain regions are formed within portions of each of the nanowires.

9. The semiconductor device of claim 1, wherein the source and drain regions of each nanowire are discrete relative to one another, the semiconductor device further comprising:

a conductive source contact surrounding each of the discrete source regions; and

a conductive drain contact surrounding each of the discrete drain regions.

10. The semiconductor device of claim 1, wherein the gate dielectric layer is a high-k gate dielectric layer, and the gate electrode is a metal gate electrode.

11. A semiconductor device, comprising:

a hetero-structure disposed above a substrate and comprising a three-dimensional semiconductor body with a channel region comprising an inner region having a first band gap and an outer cladding layer at least partially surrounding the inner region, the cladding layer having a second, narrower band gap;

a gate stack disposed on and at least partially surrounding the channel region, the gate stack comprising a gate dielectric layer disposed on the cladding layer and a gate electrode disposed on the gate dielectric layer, wherein the cladding layer only partially surrounds the inner region of the channel region, and the gate stack only partially surrounds the channel region; and

source and drain regions disposed in the three-dimensional semiconductor body, on either side of channel region.

14. The semiconductor device of claim 11, wherein the cladding layer comprises a material suitable to propagate a wave-function with low resistance.

15. The semiconductor device of claim 14, wherein the inner region of the channel region comprises a material suitable to substantially prevent current flow from source region to drain region.

16. The semiconductor device of claim 11, wherein material pairs of the cladding layer and inner region are selected from the group consisting of InP/InGaAs, GaAs/AlGaAs and AlInSb/InSb.

17. The semiconductor device of claim 11, wherein the cladding layer is germanium-rich and the inner region is silicon-rich.

18. The semiconductor device of claim 11, wherein the cladding layer has a thickness suitable to propagate a substantial portion of a wave-function and to inhibit a significant portion of the wave-function from entering the inner region of the channel region.

19. The semiconductor device of claim 18, wherein the cladding layer has a thickness approximately in the range of 50-100 Angstroms.

20. The semiconductor device of claim 11, wherein the gate dielectric layer is a high-k gate dielectric layer, and the gate electrode is a metal gate electrode.

12-13. -13. (canceled)

21. A semiconductor structure, comprising:

a first semiconductor device, comprising;

a first vertical arrangement of a plurality of nanowires disposed above a substrate, each nanowire comprising an inner region having a first band gap and an outer cladding layer surrounding the inner region, the cladding layer having a second, narrower band gap;

a first gate stack disposed on and completely surrounding a channel region of each of the nanowires, the first gate stack comprising a gate dielectric layer disposed on and surrounding the cladding layer and a gate electrode disposed on the gate dielectric layer; and

source and drain regions disposed on either side of the channel regions of the nanowires of the first vertical arrangement of the plurality of nanowires; and

a second semiconductor device, comprising;

a second vertical arrangement of a plurality of nanowires disposed above the substrate;

a second gate stack disposed on and completely surrounding a channel region of each of the nanowires, the second gate stack comprising a gate dielectric layer and a gate electrode disposed on the gate dielectric layer; and

source and drain regions disposed on either side of the channel regions of the nanowires of the second vertical arrangement of the plurality of nanowires.

22. The semiconductor structure of claim 21, wherein the first semiconductor device is an NMOS device, and the second semiconductor device is a PMOS device.

23. The semiconductor structure of claim 22, wherein the cladding layer and inner region form a group III-V material hetero-junction.

24. The semiconductor structure of claim 21, wherein each nanowire of the second semiconductor device comprises a second inner region having a first band gap and a second outer cladding layer surrounding the second inner region, the second cladding layer having a second, narrower band gap.

25. The semiconductor structure of claim 24, wherein the cladding layer and the second cladding layer each comprises a material suitable to propagate a wave-function with low resistance.

26. The semiconductor structure of claim 25, wherein the inner region and the second inner region each comprises a material suitable to substantially prevent current flow from respective source regions to drain regions.

27. The semiconductor structure of claim 24, wherein material pairs of the cladding layer and inner region are selected from the group consisting of InGaAs/InP, GaAs/AlGaAs and InSb/AlInSb, and wherein the second cladding layer is germanium-rich and the second inner region is silicon-rich.

28. The semiconductor structure of claim 24, wherein each of the cladding layer and the second cladding layer has a thickness suitable to propagate a substantial portion of a wave-function and to inhibit a significant portion of the wave-function from entering the inner region and second inner region, respectively.

29. The semiconductor structure of claim 28, wherein each of the cladding layer and the second cladding layer has a thickness approximately in the range of 50-100 Angstroms.

30. The semiconductor structure of claim 21, wherein the gate dielectric layer of the first gate stack is a high-k gate dielectric layer, and the gate electrode of the first gate stack is an N-type metal gate electrode, and wherein the gate dielectric layer of the second gate stack is a high-k gate dielectric layer, and the gate electrode of the second gate stack is a P-type metal gate electrode.

31. A semiconductor device, comprising:

a hetero-structure disposed above a substrate and comprising a three-dimensional semiconductor body with a channel region comprising an inner region having a first band gap and an outer cladding layer at least partially surrounding the inner region, the cladding layer having a second, narrower band gap, the three-dimensional semiconductor body horizontally oriented with respect to the substrate;

a gate stack disposed on and at least partially surrounding the channel region, the gate stack comprising a gate dielectric layer disposed on the cladding layer and a gate electrode disposed on the gate dielectric layer, wherein the cladding layer completely surrounds the inner region of the channel region, and the gate stack completely surrounds the channel region; and

source and drain regions disposed in the three-dimensional semiconductor body, on either side of channel region.

32. The semiconductor device of claim 31, wherein material pairs of the cladding layer and inner region are selected from the group consisting of InP/InGaAs, GaAs/AlGaAs and AlInSb/InSb.

33. The semiconductor device of claim 31, wherein the cladding layer is germanium-rich and the inner region is silicon-rich.